Inventor

MIYAYAMA YOSHIYUKI

US52 patents

⚠️ This page may combine multiple inventors who share the name “MIYAYAMA YOSHIYUKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MIYAYAMA YOSHIYUKI

SEIKO EPSON CORP

System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer

High performance, superscalar-based computer system with out-of-order instruction execution

High-performance superscalar-based computer system with out-of-order instruction execution

Method for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for handling load and/or store operations in a superscalar microprocessor

Microcomputer, electronic equipment, and debugging system

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

Data processing circuit with target instruction and prefix instruction

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

System and method for handling load and/or store operations in a superscalar microprocessor

Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the same

RISC microprocessor architecture implementing fast trap and exception state

RISC microprocessor architecture implementing fast trap and exception state

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

Data processing circuit with target instruction and prefix instruction

Microcomputer, electronic equipment, and debugging system

Method for improving pin compatibility in microcomputer emulation equipment

System and method for handling load and/or store operations in a superscalar microprocessor

Data processing circuit, microcomputer, and electronic equipment

Multiple sum-of-products circuit and its use in electronic equipment and microcomputers

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for translating non-native instructions to native instructions for processing on a host processor

High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

System and method for handling load and/or store operations in a superscalar microprocessor

Microcomputer, electronic equipment, and debugging system

TRANSMETA CORP

System and method for translating non-native instructions to native instructions for processing on a host processor

System and method for translating non-native instructions to native instructions for processing on a host processor

NGUYEN LE TRONG

High-performance, superscalar-based computer system with out-of-order instruction execution

COON BRETT

System and method for translating non-native instructions to native instructions for processing on a host processor