Inventor

GARG SANJIV

US73 patents

⚠️ This page may combine multiple inventors who share the name “GARG SANJIV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GARG SANJIV

SEIKO EPSON CORP

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

Superscalar risc instruction scheduling

High performance, superscalar-based computer system with out-of-order instruction execution

RISC microprocessor architecture implementing multiple typed register sets

RISC microprocessor architecture implementing multiple typed register sets

High-performance superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

System and method for handling load and/or store operations in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

System and method for assigning tags to control instruction processing in a superscalar processor

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

System and method for register renaming

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

System and method for assigning tags to control instruction processing in a superscalar processor

RISC microprocessor architecture implementing multiple typed register sets

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

System and method for retiring instructions in a superscalar microprocessor

System and method for register renaming

Superscalar risc instruction scheduling

RISC microprocessor architecture implementing multiple typed register sets

System and method for assigning tags to control instruction processing in a superscalar processor

System and method for assigning tags to instructions to control instruction execution

System and method for register renaming

System and method for handling load and/or store operations in a superscalar microprocessor

RISC microprocessor architecture implementing fast trap and exception state

RISC microprocessor architecture implementing fast trap and exception state

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

System and method for register renaming

System and method for assigning tags to control instruction processing in a superscalar processor

System and method for register renaming

System and method for register renaming

IADONATO KEVIN R

System and method for assigning tags to control instruction processing in a superscalar processor

TRANSMETA CORP

Superscalar RISC instruction scheduling