Inventor

HAGIWARA YASUAKI

US61 patents

⚠️ This page may combine multiple inventors who share the name “HAGIWARA YASUAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAGIWARA YASUAKI

SEIKO EPSON CORP

Microprocessor architecture capable of supporting multiple heterogeneous processors

Microprocessor architecture capable of supporting multiple heterogeneous processors

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

High performance, superscalar-based computer system with out-of-order instruction execution

Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption

High-performance superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

Microprocessor architecture capable of supporting multiple heterogeneous processors

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for handling load and/or store operations in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

System and method for adjusting priorities associated with multiple devices seeking access to a memory array unit

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Microprocessor architecture with a switch network and an arbitration unit for controlling access to memory ports

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU

System and method for handling load and/or store operations in a superscalar microprocessor

RISC microprocessor architecture implementing fast trap and exception state

RISC microprocessor architecture implementing fast trap and exception state

Microprocessor architecture capable of supporting multiple heterogeneous processors

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

Computer system for processing multiple requests and out of order returns using a request queue

System and method for processing multiple requests and out of order returns

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

System and method for handling load and/or store operations in a superscalar microprocessor

CANON KK

Zoom lens and image pickup apparatus including the same

Zoom lens and optical apparatus equipped with zoom lens

Zoom lens and image pickup apparatus having the same

Zoom lens and image pickup apparatus having the same

Zoom lens and image pickup device provided with the same

CANON KANUSHIKI KAISHA

Zoom lens and image pickup apparatus including the same

NGUYEN LE TRONG

High-performance, superscalar-based computer system with out-of-order instruction execution

HAGIWARA YASUAKI

Zoom lens and image pickup apparatus with the zoom lens