Inventor

WANG JOHANNES

US69 patents

⚠️ This page may combine multiple inventors who share the name “WANG JOHANNES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG JOHANNES

SEIKO EPSON CORP

System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

Superscalar risc instruction scheduling

System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer

High performance, superscalar-based computer system with out-of-order instruction execution

System for handling load and/or store operations in a superscalar microprocessor

High-performance superscalar-based computer system with out-of-order instruction execution

Method for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for handling load and/or store operations in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for handling load and/or store operations in a superscalar microprocessor

System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

System and method for handling load and/or store operators in a superscalar microprocessor

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

High performance, superscalar-based computer system with out-of-order instruction execution

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions

High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

System and method for retiring instructions in a superscalar microprocessor

Superscalar risc instruction scheduling

System and method for handling load and/or store operations in a superscalar microprocessor

System and method for handling load and/or store operations in a superscalar microprocessor

Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units

RISC microprocessor architecture implementing fast trap and exception state

RISC microprocessor architecture implementing fast trap and exception state

Page printer controller including a single chip superscalar microprocessor with graphics functional units

High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution

High-performance, superscalar-based computer system with out-of-order instruction execution

High-performance, superscalar-based computer system with out-of-order instruction execution

System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

System and method for handling load and/or store operations in a superscalar microprocessor

System and method for handling load and/or store operations in a superscalar microprocessor

System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor

TRANSMETA CORP

System and method for translating non-native instructions to native instructions for processing on a host processor

Superscalar RISC instruction scheduling

Superscalar RISC instruction scheduling

SEIKO CORP

Superscalar RISC instruction scheduling