Inventor

SPEAR MICHAEL B

US17 patents

⚠️ This page may combine multiple inventors who share the name “SPEAR MICHAEL B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SPEAR MICHAEL B

IBM

Power reduction in a parallel data communications interface using clock resynchronization

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Combined alignment scrambler function for elastic interface

Built-in self-test for receiver channel

System and method to inject a bit error on a bus lane

Combined alignment scrambler function for elastic interface

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Staged power on/off sequence at the I/O phy level in an interchip interface

Low-latency deserializer having fine granularity and defective-lane compensation

Double data rate (DDR) memory read latency reduction

Calibrating a quadrature receive serial interface

Power reduction in a parallel data communications interface using clock resynchronization

Reducing chip latency at a clock boundary by reference clock phase adjustment

BAUMGARTNER STEVEN J

Parallel data communications mechanism having reduced power continuously calibrated lines

BUCHMANN PETER L

Power-on initialization and test for a cascade interconnect memory system

BULZACCHELLI JOHN F

Calibration of multiple parallel data communications lines for high skew conditions

FERRAIOLO FRANK D

Dynamic fault detection and repair in a data communications mechanism