Inventor

CAPPS JR LOUIS B

US14 patents

⚠️ This page may combine multiple inventors who share the name “CAPPS JR LOUIS B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

11 patents

US7268570B1Sep 11, 2007

Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip

IBM24 citations91

US5430860AJul 4, 1995

Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence

IBM41 citations89

US7962770B2Jun 14, 2011

Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics

IBM14 citations84

US7870337B2Jan 11, 2011

Power-aware line intervention for a multiprocessor snoop coherency protocol

IBM13 citations84

US7420378B2Sep 2, 2008

Power grid structure to optimize performance of a multiple core processor

IBM12 citations83

US10025590B2Jul 17, 2018

Multicore processor and method of use that configures core functions based on executing instructions

IBM3 citations72

US9336497B2May 10, 2016

CAPPS JR LOUIS B

3 patents

US9507640B2Nov 29, 2016

Multicore processor and method of use that configures core functions based on executing instructions

CAPPS JR LOUIS B6 citations82

US8886918B2Nov 11, 2014

Dynamic instruction execution based on transaction priority tagging

CAPPS JR LOUIS B4 citations71

US8495342B2Jul 23, 2013

Configuring plural cores to perform an instruction having a multi-core characteristic

CAPPS JR LOUIS B1 citations50

CAPPS JR LOUIS B

IBM

Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip

Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence

Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics

Power-aware line intervention for a multiprocessor snoop coherency protocol

Power grid structure to optimize performance of a multiple core processor

Multicore processor and method of use that configures core functions based on executing instructions

System and method for an expert question answer system from a dynamic corpus

Personal computer memory bank parity error indicator

System, method and computer program product for data transfer management

Power grid structure to optimize performance of a multiple core processor

System and method for an expert question answer system from a dynamic corpus

CAPPS JR LOUIS B

Multicore processor and method of use that configures core functions based on executing instructions

Dynamic instruction execution based on transaction priority tagging

Configuring plural cores to perform an instruction having a multi-core characteristic