Inventor

LAI ERH-KUN

US239 patents

⚠️ This page may combine multiple inventors who share the name “LAI ERH-KUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAI ERH-KUN

MACRONIX INT CO LTD

Multi-level cell resistance random access memory with metal oxides

Bridge resistance random access memory device with a singular contact structure

Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states

Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same

Resistive memory structure with buffer layer

Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer

Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure

Method of forming a system on chip (SOC) with nitride read only memory (NROM)

Programmable resistive RAM and manufacturing method

Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same

Method of forming a MIM capacitor

3D NOR memory having vertical source and drain structures

Method for manufacturing three dimensional stacked semiconductor structure and structure manufactured by the same

Method for manufacturing 3D NAND memory using gate replacement, and resulting structures

Memory device and method for fabricating the same

Source line formation in 3D vertical channel and memory

Operation method for multi-level switching of metal-oxide based RRAM

Method for forming self-aligned thermal isolation cell for a variable resistance memory array

Air cell thermal isolation for a memory array formed of a programmable resistive material

Resistance memory with tungsten compound and manufacturing

Resistor random access memory cell device

Stacked non-volatile memory device and methods for fabricating the same

Manufacturing method for phase change RAM with electrode layer process

Operating method of non-volatile memory device

Self-aligned structure and method for confining a melting point in a resistor random access memory

Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states

Method of fabricating NROM memory cell

Method for forming a semiconductor structure

Semiconductor structure and method for manufacturing the same

Resistance type memory device and fabricating method and operating method thereof

Method of forming an embedded memory

Method of forming an NROM embedded with mixed-signal circuits

Method of forming a mixed-signal circuit embedded NROM memory and MROM memory

Method of forming MIM capacitor

Phase-change multi-level cell and operating method thereof

3D NOR memory having vertical gate structures

Reducing word line capacitance in 3D memory

Semiconductor device with memory structure

Memory device and method for operating the same

SSL/GSL gate oxide in 3D vertical channel NAND

Memory structure

LUNG HSIANG-LAN

3D memory array arranged for FN tunneling program and erase

3D memory array arranged for FN tunneling program and erase

3D two bit-per-cell NAND flash memory

Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method

Cross-point self-aligned reduced cell size phase change memory

LUE HANG-TING

Silicon on insulator and thin film transistor bandgap engineered split gate memory

CHIEN WEI-CHIH

Aluminum copper oxide based memory devices and methods for manufacture

LAI ERH-KUN

Method of a multi-level cell resistance random access memory with metal oxides

LAI ERH KUN

Method for manufacturing a resistor random access memory with a self-aligned air gap insulator