Inventor
VENTRONE SEBASTIAN THEODORE
US28 patents
⚠️ This page may combine multiple inventors who share the name “VENTRONE SEBASTIAN THEODORE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
26 patentsUS6119241ASep 12, 2000
Self regulating temperature/performance/voltage scheme for micros (X86)
IBM124 citations98
US6477654B1Nov 5, 2002
Managing VT for reduced power using power setting commands in the instruction stream
IBM160 citations97
US6345362B1Feb 5, 2002
Managing Vt for reduced power using a status table
IBM139 citations97
US5832284ANov 3, 1998
Self regulating temperature/performance/voltage scheme for micros (X86)
IBM78 citations95
US6834353B2Dec 21, 2004
Method and apparatus for reducing power consumption of a processing integrated circuit
IBM54 citations94
US6425109B1Jul 23, 2002
High level automatic core configuration
IBM73 citations92
US6026471AFeb 15, 2000
Anticipating cache memory loader and method
IBM34 citations92
US5986962ANov 16, 1999
Internal shadow latch
IBM43 citations92
US5918246AJun 29, 1999
Apparatus and method for prefetching data based on information contained in a compiler generated program map
IBM25 citations92
US5874833AFeb 23, 1999
True/complement output bus for reduced simulataneous switching noise
IBM27 citations92
US6479974B2Nov 12, 2002
Stacked voltage rails for low-voltage DC distribution
IBM33 citations91
US5867725AFeb 2, 1999
Concurrent multitasking in a uniprocessor
IBM73 citations91
US7071757B2Jul 4, 2006
Clock signal distribution utilizing differential sinusoidal signal pair
IBM12 citations83
US6141351AOct 31, 2000
Radio frequency bus for broadband microprocessor communications
IBM18 citations83
US6820254B2Nov 16, 2004
Method and system for optimizing code using an optimizing coprocessor
IBM15 citations82
US5761719AJun 2, 1998
On-chip memory map for processor cache macro
IBM17 citations76
US7454642B2Nov 18, 2008
Method and architecture for power management of an electronic device
IBM7 citations71
US6934656B2Aug 23, 2005
Auto-linking of function logic state with testcase regression list
IBM9 citations70
US7080344B2Jul 18, 2006
Coding of FPGA and standard cell logic in a tiling structure
IBM7 citations67
US8037337B2Oct 11, 2011
Structures including circuits for noise reduction in digital systems
IBM2 citations62
US7715995B2May 11, 2010
Design structure for measurement of power consumption within an integrated circuit
IBM3 citations62
US7463083B2Dec 9, 2008
Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers
IBM3 citations62
US7317348B2Jan 8, 2008
Noise reduction in digital systems
IBM3 citations62
US7831935B2Nov 9, 2010
Method and architecture for power management of an electronic device
IBM4 citations60
US6944698B2Sep 13, 2005
Method and apparatus for providing bus arbitrations in a data processing system
IBM2 citations57
US7135907B2Nov 14, 2006
Clock signal distribution utilizing differential sinusoidal signal pair
IBM0 citations51