Inventor

NOZUYAMA YASUYUKI

JP39 patents

⚠️ This page may combine multiple inventors who share the name “NOZUYAMA YASUYUKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NOZUYAMA YASUYUKI

TOSHIBA KK

Apparatus for selecting test patterns for logic circuit, computer implemented method for selecting test patterns, and computer program product for controlling a computer system so as to select test patterns

Evaluation device of weighted fault coverage and evaluation method of the same

Test-facilitating circuit for information processing devices

Method of evaluating fault coverage

Linear feedback shift register

Data transfer bus including divisional buses connectable by bus switch circuit

Semiconductor integrated circuit and its application device

Information processing system provided with self-diagnosing circuit and the self-diagnosing method therefor

Logic circuit having a control signal switching logic function and having a testing arrangement

Self-test circuit of information processor

Test system, test method and test program for an integrated circuit by IDDQ testing

Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus

Fault list and test pattern generating apparatus and method, fault list generating and fault coverage calculating apparatus and method

Apparatus for analyzing fault of semiconductor integrated circuit, method for the same, and computer readable medium for the same

Apparatus connectable to a computer network for circuit design verification, computer implemented method for circuit design verification, and computer program product for controlling a computer system so as to verify circuit designs

Signature compression circuit

Calculation system of fault coverage and calculation method of the same

Semiconductor integrated circuit device and test method thereof

Semiconductor integrated circuit device and test method thereof

Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit

Apparatus and method for minimizing the delay times in a semiconductor device

Current reduction circuit for testing purpose

Current reduction circuit for testing purpose

Testable programmable logic array

Circuit for testing circuit blocks controlled by microinstructions

Self-diagnostic circuit for logic circuit block

Test circuit for logic ICS

Semiconductor integrated circuit having function for evaluating AC performance

Apparatus for creating test pattern and calculating fault coverage or the like and method for creating test pattern and calculating fault coverage or the like

Test quality evaluating and improving system for semiconductor integrated circuit and test quality evaluation and improvement method for semiconductor integrated circuit

Data processing device with test circuit

Programmable logic arrays with each array column divided into a plurality of series connections of FETs

Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus

Method for designing semiconductor integrated circuit

NOZUYAMA YASUYUKI

Apparatus and method for calculating fault coverage, and fault detection method

Semiconductor integrated circuit and method for designing the same

Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus

Bridge fault removal apparatus, bridge fault removal method, and computer readable medium comprising computer program code for removing bridge fault

TOKYO SHIBAURA ELECTRIC CO

Test pattern selection apparatus for selecting test pattern from a plurality of check patterns