Inventor
TSAI CHAOCHIEH
TW26 patents
⚠️ This page may combine multiple inventors who share the name “TSAI CHAOCHIEH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
22 patentsUS5757045AMay 26, 1998
CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation
TAIWAN SEMICONDUCTOR MFG210 citations99
US6636139B2Oct 21, 2003
Structure to reduce the degradation of the Q value of an inductor caused by via resistance
TAIWAN SEMICONDUCTOR MFG107 citations98
US5691212ANov 25, 1997
MOS device structure and integration method
TAIWAN SEMICONDUCTOR MFG123 citations98
US5668024ASep 16, 1997
CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process
TAIWAN SEMICONDUCTOR MFG102 citations98
US6037204AMar 14, 2000
Silicon and arsenic double implanted pre-amorphization process for salicide technology
TAIWAN SEMICONDUCTOR MFG94 citations97
US6030863AFeb 29, 2000
Germanium and arsenic double implanted pre-amorphization process for salicide technology
TAIWAN SEMICONDUCTOR MFG77 citations96
US5702972ADec 30, 1997
Method of fabricating MOSFET devices
TAIWAN SEMICONDUCTOR MFG59 citations96
US6232164B1May 15, 2001
Process of making CMOS device structure having an anti-SCE block implant
TAIWAN SEMICONDUCTOR MFG124 citations95
US5674775AOct 7, 1997
Isolation trench with a rounded top edge using an etch buffer layer
TAIWAN SEMICONDUCTOR MFG79 citations94
US6943063B2Sep 13, 2005
RF seal ring structure
TAIWAN SEMICONDUCTOR MFG42 citations93
US6121139ASep 19, 2000
Ti-rich TiN insertion layer for suppression of bridging during a salicide procedure
TAIWAN SEMICONDUCTOR MFG28 citations93
US6022775AFeb 8, 2000
High effective area capacitor for high density DRAM circuits using silicide agglomeration
TAIWAN SEMICONDUCTOR MFG28 citations93
US6465294B1Oct 15, 2002
Self-aligned process for a stacked gate RF MOSFET device
TAIWAN SEMICONDUCTOR MFG31 citations92
US6444517B1Sep 3, 2002
High Q inductor with Cu damascene via/trench etching simultaneous module
TAIWAN SEMICONDUCTOR MFG58 citations92
US6245639B1Jun 12, 2001
Method to reduce a reverse narrow channel effect for MOSFET devices
TAIWAN SEMICONDUCTOR MFG47 citations92
US5821153AOct 13, 1998
Method to reduce field oxide loss from etches
TAIWAN SEMICONDUCTOR MFG20 citations92
US6171913B1Jan 9, 2001
Process for manufacturing a single asymmetric pocket implant
TAIWAN SEMICONDUCTOR MFG17 citations83
US6737310B2May 18, 2004
Self-aligned process for a stacked gate RF MOSFET device
TAIWAN SEMICONDUCTOR MFG11 citations74
US6465367B1Oct 15, 2002
Lossless co-planar wave guide in CMOS process
TAIWAN SEMICONDUCTOR MFG11 citations74
US6175125B1Jan 16, 2001
Semiconductor structure for testing vias interconnecting layers of the structure
TAIWAN SEMICONDUCTOR MFG11 citations74
US6664635B2Dec 16, 2003
Lossless microstrip line in CMOS process
TAIWAN SEMICONDUCTOR MFG2 citations57
US6495446B1Dec 17, 2002
Lossless microstrip line in CMOS process
TAIWAN SEMICONDUCTOR MFG3 citations57
TAIWAN SEMICONDUCTOR MFG CO LTD
3 patentsUS9748206B1Aug 29, 2017
Three-dimensional stacking structure and manufacturing method thereof
TAIWAN SEMICONDUCTOR MFG CO LTD41 citations91
US10777534B2Sep 15, 2020
Three-dimensional stacking structure
TAIWAN SEMICONDUCTOR MFG CO LTD8 citations81
US10157885B2Dec 18, 2018
Package structure having magnetic bonding between substrates
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations65