Inventor

LYON TERRY L

US21 patents

⚠️ This page may combine multiple inventors who share the name “LYON TERRY L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LYON TERRY L

HEWLETT PACKARD DEVELOPMENT CO

Parallel distributed function translation lookaside buffer

Masking error detection/correction latency in multilevel cache transfers

Cache chain structure to implement high bandwidth low latency cache memory subsystem

Cache connection with bypassing feature

Unified cache port consolidation

Parallel distributed function translation lookaside buffer

Method and apparatus for updating and invalidating store data

Method and apparatus for updating and invalidating store data

Masking error detection/correction latency in multilevel cache transfers

HEWLETT PACKARD CO

Method and system for early tag accesses for lower-level caches in parallel with first-level cache

Apparatus and method for virtual address aliasing and multiple page size support in a computer system having a prevalidated cache

Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design

L1 cache memory

Mechanism for broadside reads of CAM structures

IBM

Method and system in a data processing system for loading and storing vectors in a plurality of modes

Cross coupled unidirectional data ring

NAT SEMICONDUCTOR CORP

Clock signal multiplier

Serial scan diagnostics apparatus and method for a memory device

CONTROL DATA SYSTEM INC

Dual pipe cache memory with out-of-order issue capability

CONTROL DATA CORP

Data capture logic for VLSI chips

LYON TERRY L

Memory hashing for stride access