Inventor

ANDERSON TIMOTHY DAVID

US174 patents

⚠️ This page may combine multiple inventors who share the name “ANDERSON TIMOTHY DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANDERSON TIMOTHY DAVID

TEXAS INSTRUMENTS INC

Methods and apparatus to reduce bank pressure using aggressive write merging

Methods and apparatus to facilitate read-modify-write support in a victim cache

Method and apparatus to sort a vector for a bitonic sorting algorithm

Methods and apparatus to facilitate an atomic operation and/or a histogram operation in cache pipeline

Methods and apparatus for allocation in a victim cache system

Methods and apparatus to facilitate atomic operations in victim cache

Method and apparatus for vector permutation

Methods and apparatus for multi-banked victim cache with dual datapath

Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system

Methods and apparatus to facilitate write miss caching in cache system

Methods and apparatus to reduce bank pressure using aggressive write merging

One-dimensional zero padding in a stream of matrix elements

Inserting predefined pad values into a stream of vectors

Methods and apparatus to reduce read-modify-write cycles for non-aligned writes

Methods and apparatus for allocation in a victim cache system

Method and apparatus for vector sorting using vector permutation logic

Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system

Multicore shared cache operation engine

Methods and apparatus to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding

Methods and apparatus to facilitate write miss caching in cache system

Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue

Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths

Write control for read-modify-write operations in cache memory

Methods and apparatus for eviction in dual datapath victim cache system

Victim cache with write miss merging

Method and apparatus for vector based matrix multiplication

Inserting null vectors into a stream of vectors

Two-dimensional zero padding in a stream of matrix elements

Multicore shared cache operation engine

Method and apparatus for vector sorting

Multicore shared cache operation engine

Butterfly network on load data return

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in DSSS cellular systems

Streaming address generation

Vector load and duplicate operations

Controlling the number of powered vector lanes via a register field

Mechanism to queue multiple streams to run on streaming engine

Method and apparatus for dual issue multiply instructions

Methods and apparatus to reduce read-modify-write cycles for non-aligned writes

Sorting vector elements using a count value

Method and apparatus for implied bit handling in floating point multiplication

Victim cache that supports draining write-miss entries

Vector based matrix multiplication

Multiple multiplication units in a data path

Method and apparatus for vector sorting using vector permutation logic

Write merging on stores with different tags

ANDERSON TIMOTHY DAVID

Circuit which performs split precision, signed/unsigned, fixed and floating point, real and complex multiplication

Entry/exit control to/from a low power state in a complex multi level memory system

CHACHAD ABHIJEET ASHOK

Cache with multiple access pipelines