Inventor
COFLER ANDREW
FR24 patents
⚠️ This page may combine multiple inventors who share the name “COFLER ANDREW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ST MICROELECTRONICS SA
19 patentsUS6754856B2Jun 22, 2004
Memory access debug facility
ST MICROELECTRONICS SA58 citations95
US6959379B1Oct 25, 2005
Multiple execution of instruction loops within a processor without accessing program memory
ST MICROELECTRONICS SA44 citations92
US6711668B1Mar 23, 2004
Prefetch unit
ST MICROELECTRONICS SA24 citations92
US7281119B1Oct 9, 2007
Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes
ST MICROELECTRONICS SA35 citations91
US6807626B1Oct 19, 2004
Execution of a computer program
ST MICROELECTRONICS SA20 citations91
US6732276B1May 4, 2004
Guarded computer instruction execution
ST MICROELECTRONICS SA23 citations91
US6725365B1Apr 20, 2004
Branching in a computer system
ST MICROELECTRONICS SA19 citations83
US6678818B1Jan 13, 2004
Decoding next instruction of different length without length mode indicator change upon length change instruction detection
ST MICROELECTRONICS SA15 citations83
US7111152B1Sep 19, 2006
Computer system that operates in VLIW and superscalar modes and has selectable dependency control
ST MICROELECTRONICS SA11 citations82
US7496737B2Feb 24, 2009
High priority guard transfer for execution control of dependent guarded instructions
ST MICROELECTRONICS SA8 citations80
US7290089B2Oct 30, 2007
Executing cache instructions in an increased latency mode
ST MICROELECTRONICS SA12 citations79
US6889313B1May 3, 2005
Selection of decoder output from two different length instruction decoders
ST MICROELECTRONICS SA9 citations73
US6854049B2Feb 8, 2005
Method of handling instructions within a processor with decoupled architecture, in particular a processor for digital signal processing, and corresponding processor
ST MICROELECTRONICS SA6 citations63
US7240185B2Jul 3, 2007
Computer system with two debug watch modes for controlling execution of guarded instructions upon breakpoint detection
ST MICROELECTRONICS SA2 citations61
US7685470B2Mar 23, 2010
Method and device for debugging a program executed by a multitask processor
ST MICROELECTRONICS SA2 citations60
US7013256B2Mar 14, 2006
Computer system with debug facility
ST MICROELECTRONICS SA3 citations60
US7486582B2Feb 3, 2009
Dynamic memory for a cellular terminal
ST MICROELECTRONICS SA2 citations56
US7370182B2May 6, 2008
Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor
ST MICROELECTRONICS SA2 citations55
US6742131B1May 25, 2004
Instruction supply mechanism
ST MICROELECTRONICS SA1 citations52
BULL SA
4 patentsUS5596285AJan 21, 1997
Impedance adaptation process and device for a transmitter and/or receiver, integrated circuit and transmission system
BULL SA126 citations96
US5614841AMar 25, 1997
Frequency multiplier using XOR/NXOR gates which have equal propagation delays
BULL SA43 citations91
US5327031AJul 5, 1994
Variable-delay circuit
BULL SA29 citations89
US5848109ADec 8, 1998
Apparatus and process for sampling a serial digital signal
BULL SA14 citations70