Inventor
VARANASI SURYA P
US14 patents
⚠️ This page may combine multiple inventors who share the name “VARANASI SURYA P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
6 patentsUS6266091B1Jul 24, 2001
System and method for low delay mode operation video decoding
LSI LOGIC CORP40 citations92
US6101221AAug 8, 2000
Video bitstream symbol extractor for use in decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements
LSI LOGIC CORP45 citations92
US6122316ASep 19, 2000
MPEG decoding system meeting 2-frame store and letterboxing requirements
LSI LOGIC CORP18 citations83
US6289053B1Sep 11, 2001
Architecture for decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements
LSI LOGIC CORP10 citations73
US6504871B1Jan 7, 2003
IDCT processor for use in decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements
LSI LOGIC CORP11 citations72
US6236681B1May 22, 2001
Method for decoding MPEG compliant video bitstreams meeting 2-frame and letterboxing requirements
LSI LOGIC CORP10 citations72
VEXATA INC
3 patentsUS9880750B1Jan 30, 2018
Storage architecture for storage class memories
VEXATA INC28 citations91
US10140181B1Nov 27, 2018
Endurance aware raid scheme for flash based SSDS with FPGA optimized implementation
VEXATA INC2 citations66
US10134473B1Nov 20, 2018
Input output scheduling for solid state media
VEXATA INC0 citations34
BROCADE COMM SYSTEMS INC
3 patentsUS7669000B2Feb 23, 2010
Host bus adapter with multiple hosts
BROCADE COMM SYSTEMS INC27 citations87
US7430203B2Sep 30, 2008
Fibre channel zoning hardware for directing a data packet to an external processing device
BROCADE COMM SYSTEMS INC18 citations84
US9143445B2Sep 22, 2015
Method and system for link aggregation across multiple switches
BROCADE COMM SYSTEMS INC0 citations49