Inventor

TAM KING-HO

TW34 patents

⚠️ This page may combine multiple inventors who share the name “TAM KING-HO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAM KING-HO

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of generating techfile having reduced corner variation value

Characterizing cell using input waveform generation considering different circuit topologies

Automated system and method for circuit design

Automated system and method for circuit design

Layout modification method and system

Automated system and method for circuit design

Die to die interface circuit

Die to die interface circuit

Characterizing cell using input waveforms with different tail characteristics

Circuit design method and system

Voltage control of semiconductor integrated circuits

Layout modification method and system

Layout checking method for advanced double patterning photolithography with multiple spacing criteria

Semiconductor circuit design and manufacture method

GLOBAL UNICHIP CORP

Interface device and interface method for 3D semiconductor device

Semiconductor device in 3D stack with communication interface and managing method thereof

Interface for semiconductor device with symmetric bond pattern and method for arranging interface thereof

Interface for semiconductor device and interfacing method thereof

Data protection system and method thereof for 3D semiconductor device

KELLER IGOR

Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

Compact modeling of circuit stages for static timing analysis of integrated circuit designs

Methods for compact modeling of circuit stages for static timing analysis of integrated circuit designs

TAIWAN SEMICONDUCTOR MFG

Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed

System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE)

Cell characterization with Miller capacitance

KARIAT VINOD

Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model

Multi-CCC current source models and static timing analysis methods for integrated circuit designs

CADENCE DESIGN SYSTEMS INC

Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages

Static timing analysis methods for integrated circuit designs using a multi-CCC current source model

WANG CHUNG-HSING

Automatic place and route method for electromigration tolerant power distribution

KAO JERRY

System and method of electromigration avoidance for automatic place-and-route

LEE MENG-XIANG

Layout modification method and system

CHAO CHIEN-JU

Computer implemented system and method for leakage calculation