Inventor
YAO CHIH-HSIANG
TW35 patents
⚠️ This page may combine multiple inventors who share the name “YAO CHIH-HSIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
23 patentsUS8836141B2Sep 16, 2014
Conductor layout technique to reduce stress-induced void formations
TAIWAN SEMICONDUCTOR MFG105 citations98
US7081679B2Jul 25, 2006
Structure and method for reinforcing a bond pad on a chip
TAIWAN SEMICONDUCTOR MFG29 citations93
US6927498B2Aug 9, 2005
Bond pad for flip chip package
TAIWAN SEMICONDUCTOR MFG23 citations93
US7880303B2Feb 1, 2011
Stacked contact with low aspect ratio
TAIWAN SEMICONDUCTOR MFG16 citations92
US7791070B2Sep 7, 2010
Semiconductor device fault detection system and method
TAIWAN SEMICONDUCTOR MFG25 citations92
US7741714B2Jun 22, 2010
Bond pad structure with stress-buffering layer capping interconnection metal layer
TAIWAN SEMICONDUCTOR MFG36 citations92
US7592710B2Sep 22, 2009
Bond pad structure for wire bonding
TAIWAN SEMICONDUCTOR MFG19 citations92
US7265436B2Sep 4, 2007
Non-repeated and non-uniform width seal ring structure
TAIWAN SEMICONDUCTOR MFG23 citations92
US7253531B1Aug 7, 2007
Semiconductor bonding pad structure
TAIWAN SEMICONDUCTOR MFG23 citations92
US7098077B2Aug 29, 2006
Semiconductor chip singulation method
TAIWAN SEMICONDUCTOR MFG50 citations92
US7042097B2May 9, 2006
Structure for reducing stress-induced voiding in an interconnect of integrated circuits
TAIWAN SEMICONDUCTOR MFG14 citations84
US6864701B2Mar 8, 2005
Test patterns for measurement of effective vacancy diffusion area
TAIWAN SEMICONDUCTOR MFG12 citations84
US6831365B1Dec 14, 2004
Method and pattern for reducing interconnect failures
TAIWAN SEMICONDUCTOR MFG18 citations84
US7244673B2Jul 17, 2007
Integration film scheme for copper / low-k interconnect
TAIWAN SEMICONDUCTOR MFG12 citations82
US6787803B1Sep 7, 2004
Test patterns for measurement of low-k dielectric cracking thresholds
TAIWAN SEMICONDUCTOR MFG5 citations63
US6812069B2Nov 2, 2004
Method for improving semiconductor process wafer CMP uniformity while avoiding fracture
TAIWAN SEMICONDUCTOR MFG5 citations62
US7777338B2Aug 17, 2010
Seal ring structure for integrated circuit chips
TAIWAN SEMICONDUCTOR MFG6 citations61
US6787484B2Sep 7, 2004
Method of reducing visible light induced arcing in a semiconductor wafer manufacturing process
TAIWAN SEMICONDUCTOR MFG6 citations58
US6759342B2Jul 6, 2004
Method of avoiding dielectric arcing
TAIWAN SEMICONDUCTOR MFG4 citations56
US7772701B2Aug 10, 2010
Integrated circuit having improved interconnect structure
TAIWAN SEMICONDUCTOR MFG0 citations52
US7470994B2Dec 30, 2008
Bonding pad structure and method for making the same
TAIWAN SEMICONDUCTOR MFG0 citations52
US7074629B2Jul 11, 2006
Test patterns for measurement of effective vacancy diffusion area
TAIWAN SEMICONDUCTOR MFG1 citations52
US7151052B2Dec 19, 2006
Multiple etch-stop layer deposition scheme and materials
TAIWAN SEMICONDUCTOR MFG0 citations41
TAIWAN SEMICONDUCTOR MFG CO LTD
8 patentsUS9477803B2Oct 25, 2016
Method of generating techfile having reduced corner variation value
TAIWAN SEMICONDUCTOR MFG CO LTD9 citations84
US9209079B2Dec 8, 2015
Conductor layout technique to reduce stress-induced void formations
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations73
US9793212B2Oct 17, 2017
Interconnect structures and methods of forming same
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations72
US10872806B2Dec 22, 2020
Semiconductor device and manufacturing method thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10170355B2Jan 1, 2019
Semiconductor device and manufacturing method thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US10169506B2Jan 1, 2019
Circuit design method and system
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9711391B1Jul 18, 2017
Semiconductor device and manufacturing method thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9437485B2Sep 6, 2016
Method for line stress reduction through dummy shoulder structures
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51