Inventor

PALUSA CHAITANYA

US29 patents

⚠️ This page may combine multiple inventors who share the name “PALUSA CHAITANYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PALUSA CHAITANYA

LSI CORP

DSP SerDes receiver with FFE-DFE-DFFE data path

Method and apparatus for feed forward equalizer with variable cursor position

Receiver with dual clock recovery circuits

Pipelined decision feedback equalization in an interleaved serializer/deserializer receiver

Method and apparatus for pre-cursor intersymbol interference correction

Code forwarding and clock generation for transmitter repeaters

Baud rate phase detector with no error latches

Modular low power serializer-deserializer

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-tap decision feed-forward equalizer with precursor and postcursor taps

Multi-tap decision feed-forward equalizer with precursor and postcursor taps

SerDes receiver with optimized CDR pulse shaping

Serdes receiver with optimized CDR pulse shaping

SerDes receiver with optimized CDR pulse shaping

Multi-tap decision feed-forward equalizer with precursor and postcursor taps

Multi-tap decision feed-forward equalizer with precursor and postcursor taps

ORACLE INT CORP

Baseline wander correction gain adaptation

Baud-rate clock data recovery with improved tracking performance

SERDES built-in sinusoidal jitter injection

Adaptive receiver with pre-cursor cancelation

Adapative receiver with pre-cursor cancelation

Adaptive receiver with pre-cursor cancelation

ALLIANCE SEMICONDUCTOR CORP

Bootstrapped charge pump

Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings

LSI LOGIC CORP

IDDQ test methodology based on the sensitivity of fault current to power supply variations

IDDQ test methodology based on the sensitivity of fault current to power supply variations

DONG YIKUI JEN

Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage

PALUSA CHAITANYA

Decision feedforward equalization

ALLIANCE SEMICONDUCTOR

Ultra low power voltage translation circuitry and its application in a TTL-to-CMOS buffer

PROKOP TOMASZ

Sparse and reconfigurable floating tap feed forward equalization