Inventor

MUELLER SILVIA M

DE69 patents

⚠️ This page may combine multiple inventors who share the name “MUELLER SILVIA M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUELLER SILVIA M

IBM

Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation

Normalization of a product on a datapath

Inference based condition code generation

Digit validation check control in instruction execution

Negative zero control in instruction execution

Residue prediction of packed data

Very low precision floating point representation for deep learning acceleration

Inference based condition code generation

Inference based condition code generation

System and method for storing numbers in first and second formats in a register file

Fused-multiply-add floating-point operations on 128 bit wide operands

Multiply-add operations of binary numbers in an arithmetic unit

Fused multiply add pipeline

Residue prediction of packed data

Using error correcting codes for parity purposes

Multiply-add operations of binary numbers in an arithmetic unit

Arithmetic operation in a data processing system

Performing processing using hardware counters in a computer system

Wide vector execution in single thread mode for an out-of-order processor

Wide vector execution in single thread mode for an out-of-order processor

Normalization of a product on a datapath

Normalization of a product on a datapath

Overflow detection for sign-magnitude adders

Residue prediction of packed data

Decimal and binary floating point rounding

Overflow detection for sign-magnitude adders

Decimal and binary floating point rounding

Residue-based checking of a shift operation

Decimal and binary floating point rounding

Parallel decimal multiplication hardware with a 3x generator

Multiply-add operations of binary numbers in an arithmetic unit

Inference based condition code generation

Tiny detection in a floating-point unit

Temporary pipeline marking for processor error workarounds

Parallel decimal multiplication hardware with a 3X generator

Tiny detection in a floating-point unit

Non-local error detection in processor systems

Arithmetic operation in a data processing system

Splitable and scalable normalizer for vector data

Optimized structure for hexadecimal and binary multiplier array

Non-local error detection in processor systems

Temporary pipeline marking for processor error workarounds

Temporary pipeline marking for processor error workarounds

BOERSMA MAARTEN J

Supporting multiple formats in a floating point processor

Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency

Fast floating point compare with slower backup for corner cases

Fused multiply-adder with booth-encoding

BAROWSKI HARRY S

Zero indication forwarding for floating point unit power reduction

Zero indication forwarding for floating point unit power reduction

CARLOUGH STEVEN R

Decimal adder with end around carry