Inventor

GAUR JAYESH

IN30 patents

⚠️ This page may combine multiple inventors who share the name “GAUR JAYESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GAUR JAYESH

INTEL CORP

Application programming interface for fine grained low latency decompression within processor core

Cryptographic computing engine for memory load and store units of a microarchitecture pipeline

Technology for dynamically tuning processor features

Memory-efficient last level cache architecture

Memory-efficient last level cache architecture

Data relocation for inline metadata

Automatic predication of hard-to-predict convergent branches

Efficient hardware-based extraction of program instructions for critical paths

Using data pattern to mark cache lines as invalid

Device, method and system to predict an address collision by a load and a store

Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time

Partner-aware virtual microsectoring for sectored cache architectures

System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processor

Instruction and micro-architecture support for decompression on core

Technology for dynamically tuning processor features

Detecting a dynamic control flow re-convergence point for conditional branches in hardware

Technology for dynamically tuning processor features

Criticality based port scheduling

High bandwidth destructive read embedded memory

Memory aware reordered source

Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP)

Data compression in processor caches

Multi-level system memory with near memory capable of storing compressed cache lines

Compressed cache memory with decompress on fault

System, apparatus and method for focused data value prediction to accelerate focused instructions

Device, method, and system to facilitate improved bandwidth of a branch prediction unit

Apparatus and method for hardware-based memoization of function calls to reduce instruction execution

GAUR JAYESH

Bypass and insertion algorithms for exclusive last-level caches

SRINIVASAN SURESH

Online learning based algorithms to increase retention and reuse of GPU-generated dynamic surfaces in outer-level caches

ALAMELDEEN ALAA R

Cache memory data compression and decompression