Inventor
MORIMOTO SEIICHI
US16 patents
⚠️ This page may combine multiple inventors who share the name “MORIMOTO SEIICHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
9 patentsUS6081272AJun 27, 2000
Merging dummy structure representations for improved distribution of artifacts in a semiconductor layer
INTEL CORP59 citations94
US5127196AJul 7, 1992
Apparatus for planarizing a dielectric formed over a semiconductor substrate
INTEL CORP96 citations94
US5104828AApr 14, 1992
Method of planarizing a dielectric formed over a semiconductor substrate
INTEL CORP75 citations94
US5672095ASep 30, 1997
Elimination of pad conditioning in a chemical mechanical polishing process
INTEL CORP45 citations92
US5081051AJan 14, 1992
Method for conditioning the surface of a polishing pad
INTEL CORP206 citations92
US4721548AJan 26, 1988
Semiconductor planarization process
INTEL CORP46 citations92
US5911111AJun 8, 1999
Polysilicon polish for patterning improvement
INTEL CORP18 citations84
US7084053B2Aug 1, 2006
Unidirectionally conductive materials for interconnection
INTEL CORP5 citations73
US7405419B2Jul 29, 2008
Unidirectionally conductive materials for interconnection
INTEL CORP1 citations51