Inventor
HOU YUNG-CHIN
TW34 patents
⚠️ This page may combine multiple inventors who share the name “HOU YUNG-CHIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
11 patentsUS8001494B2Aug 16, 2011
Table-based DFM for accurate post-layout analysis
TAIWAN SEMICONDUCTOR MFG16 citations92
US7808051B2Oct 5, 2010
Standard cell without OD space effect in Y-direction
TAIWAN SEMICONDUCTOR MFG29 citations92
US7821039B2Oct 26, 2010
Layout architecture for improving circuit performance
TAIWAN SEMICONDUCTOR MFG30 citations91
US7932566B2Apr 26, 2011
Structure and system of mixing poly pitch cell design under default poly pitch design rules
TAIWAN SEMICONDUCTOR MFG15 citations83
US7458051B2Nov 25, 2008
ECO cell for reducing leakage power
TAIWAN SEMICONDUCTOR MFG14 citations83
US7797668B2Sep 14, 2010
Method for optimally converting a circuit design into a semiconductor device
TAIWAN SEMICONDUCTOR MFG2 citations63
US7401302B2Jul 15, 2008
System on chip development with reconfigurable multi-project wafer technology
TAIWAN SEMICONDUCTOR MFG2 citations62
US7350177B2Mar 25, 2008
Configurable logic and memory devices
TAIWAN SEMICONDUCTOR MFG6 citations62
US7467365B2Dec 16, 2008
Sanity checker for integrated circuits
TAIWAN SEMICONDUCTOR MFG5 citations58
US7913141B2Mar 22, 2011
Power gating in integrated circuits for leakage reduction
TAIWAN SEMICONDUCTOR MFG4 citations57
US8671382B2Mar 11, 2014
Method of generating RC technology file
TAIWAN SEMICONDUCTOR MFG1 citations52
TAIWAN SEMICONDUCTOR MFG CO LTD
11 patentsUS10678973B2Jun 9, 2020
Machine-learning design enablement platform
TAIWAN SEMICONDUCTOR MFG CO LTD13 citations85
US11113443B1Sep 7, 2021
Integrated circuit with thicker metal lines on lower metallization layer
TAIWAN SEMICONDUCTOR MFG CO LTD6 citations83
US11017149B2May 25, 2021
Machine-learning design enablement platform
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US11593546B2Feb 28, 2023
Integrated circuit with thicker metal lines on lower metallization layer
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations72
US12094880B2Sep 17, 2024
Integrated circuits and manufacturing methods thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12008302B2Jun 11, 2024
Integrated circuit with thicker metal lines on lower metallization layer
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11581314B2Feb 14, 2023
Integrated circuits and manufacturing methods thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US12557393B2Feb 17, 2026
Method of semiconductor layout with different row heights
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US11682665B2Jun 20, 2023
Semiconductor layout with different row heights
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations61
US10535655B2Jan 14, 2020
Integrated circuits and manufacturing methods thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9811627B2Nov 7, 2017
Method of component partitions on system on chip and device thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
HOU YUNG-CHIN
6 patentsUS8507957B2Aug 13, 2013
Integrated circuit layouts with power rails under bottom metal layer
HOU YUNG-CHIN30 citations92
US8504972B2Aug 6, 2013
Standard cells having flexible layout architecture/boundaries
HOU YUNG-CHIN21 citations92
US8631366B2Jan 14, 2014
Integrated circuit design using DFM-enhanced architecture
HOU YUNG-CHIN10 citations83
US8217469B2Jul 10, 2012
Contact implement structure for high density design
HOU YUNG-CHIN17 citations83
US8431985B2Apr 30, 2013
Layout and process of forming contact plugs
HOU YUNG-CHIN6 citations73
US8201111B2Jun 12, 2012
Table-based DFM for accurate post-layout analysis
HOU YUNG-CHIN1 citations51