Inventor
UEMURA TERUO
JP5 patents
Patents
5 patentsUS5321287AJun 14, 1994
Semiconductor device wherein n-channel MOSFET, p-channel MOSFET and nonvolatile memory cell are formed in one chip
TOSHIBA KK81 citations94
US5223451AJun 29, 1993
Semiconductor device wherein n-channel MOSFET, p-channel MOSFET and nonvolatile memory cell are formed in one chip and method of making it
TOSHIBA KK36 citations90
US5200636AApr 6, 1993
Semiconductor device having E2 PROM and EPROM in one chip
TOSHIBA KK32 citations90
US5219775AJun 15, 1993
Manufacturing method for a floating gate semiconductor memory device by forming cell slits
TOSHIBA KK6 citations61
US5319594AJun 7, 1994
Semiconductor memory device including nonvolatile memory cells, enhancement type load transistors, and peripheral circuits having enhancement type transistors
TOSHIBA KK2 citations59