Inventor

BRATT JOSEPH P

US62 patents

⚠️ This page may combine multiple inventors who share the name “BRATT JOSEPH P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRATT JOSEPH P

APPLE INC

Deferred shading graphics pipeline processor having advanced features

Method for variable length decoding using multiple configurable look-up tables

Method and apparatus for data processing

Raw scaler with chromatic aberration correction

Chroma cache architecture in block processing pipelines

Systems and methods for local tone mapping

Hardware-based power management of functional blocks

Method and apparatus for vector table look-up

Method and apparatus for selectively switching IC ports to card slots through the use of three switches per switch group

Clock control for DMA busses

Raw scaler with chromatic aberration correction

Raw scaler with chromatic aberration correction

Buffer underrun handling

Data storage and access in block processing pipelines

Parameter FIFO

Raw scaler with chromatic aberration correction

Method and apparatus for computing vector absolute differences

APPLE COMPUTER

Graphics processor with pipeline state storage and retrieval

Graphics processor with pipeline state storage and retrieval

Deferred shading graphics pipeline processor having advanced features

Deferred shading graphics pipeline processor having advanced features

Graphics processor with deferred shading

Deferred shading graphics pipeline processor

Deferred shading graphics pipeline processor

Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor

Method and apparatus for address re-mapping

Method and apparatus for memory access

Method and apparatus for matrix transposition

Apparatus for parallel vector table look-up

Pipelining cache-coherence operations in a shared-memory multiprocessing system

Memory controller chipset

Method and apparatus for forming and dispatching instruction groups based on priority comparisons

COTE GUY

Image signal processor line buffer configuration for processing ram image data

Dual image sensor image processing system and method

Systems and methods for RGB image processing

Systems and methods for YCC image processing

Systems and methods for raw image processing

Binning compensation filtering techniques for image signal processing

Image signal processing involving geometric distortion correction

Image sensor data formats and memory addressing techniques for image signal processing

SILICON GRAPHICS INC

System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes

Debug mode for a superscalar RISC processor

Conflict resolution in interleaved memory systems with multiple parallel accesses

Method for preventing multi-level cache system deadlock in a multi-processor system

BRATT JOSEPH P

Reproducible dither-noise injection

Streaming translation in display pipe

Buffer underrun handling

LIM SUK HWAN

Systems and methods for local tone mapping

Local image statistics collection

CONROY DAVID G

Clock control for DMA busses