Inventor
SEGAL RUSSELL B
US18 patents
Patents
18 patentsUS6496972B1Dec 17, 2002
Method and system for circuit design top level and block optimization
SYNOPSYS INC70 citations96
US5530841AJun 25, 1996
Method for converting a hardware independent user description of a logic circuit into hardware components
SYNOPSYS INC32 citations95
US6678644B1Jan 13, 2004
Integrated circuit models having associated timing exception information therewith for use with electronic design automation
SYNOPSYS INC49 citations92
US6438731B1Aug 20, 2002
Integrated circuit models having associated timing exception information therewith for use in circuit design optimizations
SYNOPSYS INC38 citations92
US6023568AFeb 8, 2000
Extracting accurate and efficient timing models of latch-based designs
SYNOPSYS INC44 citations92
US5790830AAug 4, 1998
Extracting accurate and efficient timing models of latch-based designs
SYNOPSYS INC36 citations92
US5661661AAug 26, 1997
Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof
SYNOPSYS INC19 citations92
US9189591B2Nov 17, 2015
Path-based floorplan analysis
SYNOPSYS INC9 citations84
US6317863B1Nov 13, 2001
Method and apparatus for irregular datapath placement in a datapath placement tool
SYNOPSYS INC18 citations84
US9460258B2Oct 4, 2016
Shaping integrated with power network synthesis (PNS) for power grid (PG) alignment
SYNOPSYS INC7 citations82
US5748488AMay 5, 1998
Method for generating a logic circuit from a hardware independent user description using assignment conditions
SYNOPSYS INC15 citations81
US5691911ANov 25, 1997
Method for pre-processing a hardware independent description of a logic circuit
SYNOPSYS INC10 citations81
US5581781ADec 3, 1996
Synthesizer for generating a logic network using a hardware independent description
SYNOPSYS INC13 citations81
US5953235ASep 14, 1999
Method for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereof
SYNOPSYS INC8 citations73
US5680318AOct 21, 1997
Synthesizer for generating a logic network using a hardware independent description
SYNOPSYS INC3 citations73
US5737574AApr 7, 1998
Method for generating a logic circuit from a hardware independent user description using mux conditions and hardware selectors
SYNOPSYS INC1 citations62
US9754070B2Sep 5, 2017
Path-based floorplan analysis
SYNOPSYS INC1 citations52
US9026974B2May 5, 2015
Semiconductor integrated circuit partitioning and timing
SYNOPSYS INC0 citations35