Inventor
KHAN LAIQUE
US3 patents
Patents
3 patentsUS5963801AOct 5, 1999
Method of forming retrograde well structures and punch-through barriers using low energy implants
LSI LOGIC CORP60 citations94
US5877530AMar 2, 1999
Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation
LSI LOGIC CORP44 citations91
US6180470B1Jan 30, 2001
FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elements
LSI LOGIC CORP15 citations82