Inventor
LAI YEONG-CHIH
TW8 patents
Patents
8 patentsUS6103619AAug 15, 2000
Method of forming a dual damascene structure on a semiconductor wafer
UNITED MICROELECTRONICS CORP114 citations96
US6239043B1May 29, 2001
Method for modulating uniformity of deposited layer thickness
UNITED MICROELECTRONICS CORP26 citations91
US6204096B1Mar 20, 2001
Method for reducing critical dimension of dual damascene process using spin-on-glass process
UNITED MICROELECTRONICS CORP24 citations91
US6255162B1Jul 3, 2001
Method of gap filling
UNITED MICROELECTRONICS CORP15 citations82
US6239024B1May 29, 2001
Method of filling gap with dielectrics
UNITED MICROELECTRONICS CORP7 citations72
US6284645B1Sep 4, 2001
Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process
UNITED MICROELECTRONICS CORP3 citations61
US6248662B1Jun 19, 2001
Method of improving gap filling characteristics of dielectric layer by implantation
UNITED MICROELECTRONICS CORP2 citations61
US6133131AOct 17, 2000
Method of forming a gate spacer on a semiconductor wafer
UNITED MICROELECTRONICS CORP6 citations61