Inventor

O'CONNOR DENNIS M

US59 patents

⚠️ This page may combine multiple inventors who share the name “O'CONNOR DENNIS M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

O'CONNOR DENNIS M

INTEL CORP

Method of time shifting to simultaneously record and play a data stream

Method and apparatus to steer memory access operations in a virtual memory system

Digital image sensor with low device count per pixel analog-to-digital conversion

High-speed starvation-free arbiter system, rotating-priority arbiter, and two stage arbitration method

Time shifting by concurrently recording and playing a data stream

System for protecting memory accesses by comparing the upper and lower bounds addresses and attribute bits identifying unauthorized combinations of type of operation and mode of access

System for protecting unauthorized memory accesses by comparing base memory address with mask bits and having attribute bits for identifying access operational mode and type

Resource management in security enhanced processors

Multi-bit scoreboarding to handle write-after-write hazards and eliminate bypass comparators

Strobe compatible digital image sensor with low device count per pixel analog-to-digital conversion

Disk head assembly with multiple read and/or write transducers for improved performance

Tipping indicator

Method and apparatus for accommodating different issue width implementations of VLIW architectures

Time shifting by concurrently recording and playing an audio stream

Predecode apparatus, systems, and methods

Transmitting signals to cause replays to be recorded at a plurality of receivers

Method and apparatus to encode digital signals

Planar waveguide and method of forming the same

Active digital audio/video signal modification to correct for playback system deficiencies

Method and apparatus for increasing throughput when accessing registers by using multi-bit scoreboarding with a bypass control unit

Method and apparatus for speeding sequential access of a set-associative cache

Disk head assembly with multiple read and/or write transducers for improved performance

Method of providing and retrieving a data segment

Method and apparatus to enable execution of a thread in a multi-threaded computer system

Apparatus and method to share a cache memory

Planar waveguide and method of forming the same

Programmable transaction initiator architecture for systems with secure and non-secure modes

Address conversion technique in a context switching environment

O'CONNOR DENNIS M

Techniques to share multimedia and enable cellular phone conference calling using ad-hoc wireless networks

Moveable locked lines in a multi-level cache

Secure memory controller

Architecture for virtual security module

Secure controller for block oriented storage

Methods and apparatus to selectively power functional units

Storage of video stream multiplexed with random access playback after variable time delay

Methods and apparatus to selectively power functional units

Secure controller for block oriented storage

Low locality-of-reference support in a multi-level cache hierachy

MARVELL INT LTD

Methods and apparatus to selectively power functional units

Serially indexing a cache memory

Translation lookaside buffer prediction mechanism

Methods and apparatus to selectively power functional units

Physically-tagged cache with virtual fill buffers

Physically-tagged cache with virtually-tagged fill buffers

Serially indexing a cache memory

Translation lookaside buffer prediction mechanism

Translation lookaside buffer prediction mechanism

Register file with integrated routing to execution units for multi-threaded processors

MICRON TECHNOLOGY INC

Architecture for virtual security module

Secure controller for block oriented storage