Inventor

LII MIRNG-JI

TW228 patents

⚠️ This page may combine multiple inventors who share the name “LII MIRNG-JI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LII MIRNG-JI

TAIWAN SEMICONDUCTOR MFG CO LTD

Integrated circuit package and methods of forming same

Substrate design for semiconductor packages and method of forming same

Substrate design for semiconductor packages and method of forming same

Multi-die package with bridge layer and method for making the same

Package-on-package structure with organic interposer

Wafer level package structure and method of forming same

Conical-shaped or tier-shaped pillar connections

Substrate design for semiconductor packages and method of forming same

Package structures and methods for forming the same

Packages with stacked dies and methods of forming the same

Hybrid interconnect for chip stacking

Wafer level package structure and method of forming same

Package on-package (PoP) structure including stud bulbs

Package on package structure and method for forming the same

Thermal performance structure for semiconductor packages and method of forming same

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

TAIWAN SEMICONDUCTOR MFG

Fan-out interconnect structure and method for forming same

Packages with stacked dies and methods of forming the same

System and method for an improved interconnect structure

System and method for an improved fine pitch joint

Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads

Thermally enhanced wafer level package

Stratified underfill in an IC package

Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade

Overhang support for a stacked semiconductor device, and method of forming thereof

Pop joint through interposer

3D package with through substrate vias

Semiconductor device with post-passivation interconnect structure and method of forming the same

Method of making a semiconductor device having a post-passivation interconnect structure

Semiconductor structure and manufacturing method thereof

YU CHEN-HUA

Package-on-package (PoP) structure including stud bulbs and method

Package on package devices and methods of packaging semiconductor dies

Package on package devices and methods of forming same

Package on package structures and methods for forming the same

Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material

INTEL CORP

Energy-absorbing stable guard ring

Substrate for reducing electromagnetic interference and enclosure

C4 package die backside coating

Integrated circuit package with surface mounted pins on an organic substrate and method of fabrication therefor

CHEN HSIEN-WEI

Post-passivation interconnect structure

Wafer-level chip scale package with re-workable underfill

PU HAN-PING

Wafer level package structure and fabrication methods

SHAO TUNG-LIANG

Apparatus and methods for forming through vias

LIN CHIH-WEI

Packaging methods and structures for semiconductor devices

KUO TIN-HAO

Conical-shaped or tier-shaped pillar connections

WANG TSUNG-DING

Package on package devices and methods of packaging semiconductor dies

LU WEN-HSIUNG

Forming wafer-level chip scale package structures with reduced number of seed layers

TSAI PEI-CHUN

Connecting function chips to a package to form package-on-package

LIANG SHIH-WEI

Post-passivation interconnect structure

TAIWAN SEMCONDUCTOR MFG CO LTD

Fixture for P-through silicon via assembly