Inventor

PELEG ALEXANDER

IL40 patents

⚠️ This page may combine multiple inventors who share the name “PELEG ALEXANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PELEG ALEXANDER

INTEL CORP

Processor executing unpack instruction to interleave data elements from two packed data

Method for unpacking a plurality of packed data into a result packed data

Microprocessor capable of unpacking packed data

Method and apparatus for performing multiply-subtract operations on packed data

Method of sorting numbers to obtain maxima/minima values with ordering

Method for packing a plurality of packed data elements in response to a pack instruction

Processor performing packed data multiplication

Method for performing shift operations on packed data

Microprocessor capable of unpacking packed data in response to a unpack instruction

Apparatus for performing multiply-add operations on packed data

Dynamic flow instruction cache memory organized around trace segments independent of virtual address line

System and method for fusing instructions

Processor for performing shift operations on packed data

Method for multiplying packed data

Method and apparatus to support an expanded register set

Method and apparatus for executing a 32-bit application by confining the application to a 32-bit address space subset in a 64-bit processor

Processor for performing multiply-add operations on packed data

System and method for fusing instructions

Method of sorting numbers to obtain maxima/minima values with ordering

Method for performing population counts on packed data types

Method of sorting signed numbers and solving absolute differences using packed instructions

Method for performing multiply-substrate operations on packed data

Processor executing unpack and pack instructions specifying two source packed data operands and saturation

Packing lower half bits of signed data elements in two source registers in a destination register with saturation

Method and apparatus for unpacking and moving packed data

Interleaving saturated lower half of data elements from two source registers of packed data

Processor for performing multiply-add operations on packed data

Method and apparatus to support an expanded register set

PELEG ALEXANDER

Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register

Processor for performing multiply-add operations on packed data

Enclosed structures

Sheltering structures and a method of assembling same

Fastening devices for flexible sheets

Packing two packed signed data in registers with saturation

Packing signed word elements from two source registers to saturated signed byte elements in destination register

Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation

Processor executing pack and unpack instructions

Method and apparatus for performing multiply-add operations on packed data

Processor for performing multiply-add operations on packed data

RONEN RONNY

Compiler-directed sign/zero extension of a first bit size result to overwrite incorrect data before subsequent processing involving the result within an architecture supporting larger second bit size values