Inventor

MENNEMEIER LARRY M

US71 patents

⚠️ This page may combine multiple inventors who share the name “MENNEMEIER LARRY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MENNEMEIER LARRY M

INTEL CORP

Processor executing unpack instruction to interleave data elements from two packed data

Method for performing multiply-add operations on packed data

Method for unpacking a plurality of packed data into a result packed data

Microprocessor capable of unpacking packed data

Method and apparatus for performing multiply-subtract operations on packed data

Method and apparatus for performing multiply-add operations on packed data

Method and apparatus for multiplying and accumulating data samples and complex coefficients

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations

Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner

Method for packing a plurality of packed data elements in response to a pack instruction

Processor performing packed data multiplication

Method for performing shift operations on packed data

Microprocessor capable of unpacking packed data in response to a unpack instruction

Apparatus for performing multiply-add operations on packed data

Apparatus for performing multiply-add operations on packed data

Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file

Apparatus for performing packed shift operations

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Apparatus for performing packed shift operations

Method for executing instructions that operate on different data types stored in the same single logical register file

System for signal processing using multiply-add operations

Computer system for performing complex digital filters

Computer implemented method for transferring packed data between register files and memory

Method and apparatus for providing high numerical accuracy with packed multiply-add or multiply-subtract operations

Processor for performing shift operations on packed data

Method for transposing a two-dimensional array

Manipulating video and audio signals using a processor which supports SIMD instructions

Executing different instructions that cause different data type operations to be performed on single logical register file

Method for multiplying packed data

Method and apparatus for a single instruction multiple data early-out zero-skip multiplier

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Computer system performing a two-dimensional rotation of packed data representing multimedia information

Method for performing complex fast fourier transforms (FFT&#39;s)

Processor for performing multiply-add operations on packed data

Method and apparatus for performing multiply-add operations on packed data

Processor with instructions that operate on different data types stored in the same single logical register file

System for providing the absolute difference of unsigned values

Method for performing multiply-substrate operations on packed data

Method and an apparatus for providing the absolute difference of unsigned values

Method and apparatus for performing packed shift operations

Method and apparatus for performing multiply-add operations on packed data

Method and apparatus for providing packed shift operations in a processor

Method and apparatus for providing packed shift operations in a processor

Method and apparatus for providing packed shift operations in a processor

Processor capable of executing packed shift operations

PELEG ALEXANDER

Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register

Processor for performing multiply-add operations on packed data

Packing two packed signed data in registers with saturation

PELEG ALEXANDER D

Processor for performing multiply-add operations on packed data

Method for performing complex fast fourier transforms (FFT's)