Inventor
MOORE CHARLES ROBERTS
US17 patents
Patents
17 patentsUS6728866B1Apr 27, 2004
Partitioned issue queue and allocation strategy
IBM122 citations98
US5724565AMar 3, 1998
Method and system for processing first and second sets of instructions by first and second types of processing systems
IBM200 citations98
US6609190B1Aug 19, 2003
Microprocessor with primary and secondary issue queue
IBM58 citations96
US6766442B1Jul 20, 2004
Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value
IBM46 citations92
US6748519B1Jun 8, 2004
Method and apparatus for utilizing renamed registers based upon a functional or defective operational status of the register
IBM33 citations92
US6725354B1Apr 20, 2004
Shared execution unit in a dual core processor
IBM50 citations92
US6678820B1Jan 13, 2004
Processor and method for separately predicting conditional branches dependent on lock acquisition
IBM29 citations92
US6662294B1Dec 9, 2003
Converting short branches to predicated instructions
IBM47 citations92
US6654869B1Nov 25, 2003
Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling
IBM43 citations92
US6625746B1Sep 23, 2003
Microprocessor instruction buffer redundancy scheme
IBM23 citations92
US5706464AJan 6, 1998
Method and system for achieving atomic memory references in a multilevel cache data processing system
IBM48 citations92
US5848283ADec 8, 1998
Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization
IBM23 citations88
US6938148B2Aug 30, 2005
Managing load and store operations using a storage management unit with data flow architecture
IBM15 citations82
US6658555B1Dec 2, 2003
Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline
IBM12 citations74
US6658558B1Dec 2, 2003
Branch prediction circuit selector with instruction context related condition type determining
IBM12 citations74
US5793986AAug 11, 1998
Method and system for enhanced efficiency of data transfers from memory to multiple processors in a data processing system
IBM5 citations62
US5692218ANov 25, 1997
System for transferring data between input/output devices having separate address spaces in accordance with initializing information in address packages
IBM2 citations60