Inventor
KNAACK ROLAND T
US20 patents
⚠️ This page may combine multiple inventors who share the name “KNAACK ROLAND T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CYPRESS SEMICONDUCTOR CORP
13 patentsUS5872802AFeb 16, 1999
Parity generation and check circuit and method in read data path
CYPRESS SEMICONDUCTOR CORP38 citations92
US5852748ADec 22, 1998
Programmable read-write word line equality signal generation for FIFOs
CYPRESS SEMICONDUCTOR CORP20 citations92
US5777944AJul 7, 1998
Circuit and method for instruction controllable slewrate of bit line driver
CYPRESS SEMICONDUCTOR CORP33 citations92
US6023777AFeb 8, 2000
Testing method for devices with status flags
CYPRESS SEMICONDUCTOR CORP16 citations84
US5764967AJun 9, 1998
Multiple frequency memory array clocking scheme for reading and writing multiple width digital words
CYPRESS SEMICONDUCTOR CORP17 citations84
US5682356AOct 28, 1997
Multiple word width memory array clocking scheme for reading words from a memory array
CYPRESS SEMICONDUCTOR CORP15 citations82
US6005821ADec 21, 1999
Circuit and method for instruction controllable slew rate of bit line driver
CYPRESS SEMICONDUCTOR CORP15 citations81
US5968190AOct 19, 1999
Redundancy method and circuit for self-repairing memory arrays
CYPRESS SEMICONDUCTOR CORP14 citations73
US5898315AApr 27, 1999
Output buffer circuit and method having improved access
CYPRESS SEMICONDUCTOR CORP11 citations73
US5712820AJan 27, 1998
Multiple word width memory array clocking scheme
CYPRESS SEMICONDUCTOR CORP11 citations73
US6510486B1Jan 21, 2003
Clocking scheme for independently reading and writing multiple width words from a memory array
CYPRESS SEMICONDUCTOR CORP5 citations63
US5828617AOct 27, 1998
Multiple word width memory array clocking scheme for reading words from a memory array
CYPRESS SEMICONDUCTOR CORP3 citations62
US5812465ASep 22, 1998
Redundancy circuit and method for providing word lines driven by a shift register
CYPRESS SEMICONDUCTOR CORP2 citations54
INTEGRATED DEVICE TECH
6 patentsUS7079446B2Jul 18, 2006
DRAM interface circuits having enhanced skew, slew rate and impedance control
INTEGRATED DEVICE TECH90 citations96
US6173425B1Jan 9, 2001
Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams
INTEGRATED DEVICE TECH77 citations94
US5978307ANov 2, 1999
Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same
INTEGRATED DEVICE TECH47 citations92
US7082071B2Jul 25, 2006
Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes
INTEGRATED DEVICE TECH16 citations79
US7196562B1Mar 27, 2007
Programmable clock drivers that support CRC error checking of configuration data during program restore operations
INTEGRATED DEVICE TECH10 citations74
US7120075B1Oct 10, 2006
Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching
INTEGRATED DEVICE TECH2 citations60