Inventor

GRIDER DOUGLAS T

US43 patents

⚠️ This page may combine multiple inventors who share the name “GRIDER DOUGLAS T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRIDER DOUGLAS T

TEXAS INSTRUMENTS INC

Method of forming thin silicon nitride or silicon oxynitride gate dielectrics

Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile

Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates

Disposable spacer technology for reduced cost CMOS processing

Doped polysilicon to retard boron diffusion into and through thin gate dielectrics

Disposable spacer technology for reduced cost CMOS processing

PMD liner nitride films and fabrication methods for improved NMOS performance

Method for transistor gate dielectric layer with uniform nitrogen concentration

Semiconductor device isolation structure and method of forming

Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile

Integrated circuit isolation

Selective area halogen doping to achieve dual gate oxide thickness on a wafer

Gate fabrication processes for split-gate transistors

Drive current improvement from recessed SiGe incorporation close to gate

Reliable high voltage gate dielectric layers using a dual nitridation process

Reliable high voltage gate dielectric layers using a dual nitridation process

Multi-layered polysilicon process

Nitrogen based implants for defect reduction in strained silicon

Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps

High performance CMOS transistors using PMD liner stress

Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps

Source/drain extension fabrication process with direct implantation

Partially disposed gate layer into the trenches

Integrated circuit including vertical capacitors

Integrated circuit including vertical capacitors

Method of fabricating a shallow doped region for a shallow junction transistor

Transistors with dual wells

Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates

Method to reduce boron diffusion through gate oxide using sidewall spacers

High tilt angle plus twist drain extension implant for CHC lifetime improvement

Three dimensional three semiconductor high-voltage capacitors

High tilt angle plus twist drain extension implant for CHC lifetime improvement

Partially disposed gate layer into the trenches

Transistors with dual wells

LSI LOGIC CORP

Product resulting from selective deposition of polysilicon over single crystal silicon substrate

Process for selective deposition of polysilicon over single crystal silicon substrate and resulting product

Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device

Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device

UNIV NORTH CAROLINA STATE

Selective deposition of doped silion-germanium alloy on semiconductor substrate

Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures

BU HAOWEN

High performance CMOS transistors using PMD liner stress

PMD liner nitride films and fabrication methods for improved NMOS performance

CHAKRAVARTHI SRINIVASAN

Nitrogen based implants for defect reduction in strained silicon