Inventor
PANDA SIDDHARTHA
US32 patents
⚠️ This page may combine multiple inventors who share the name “PANDA SIDDHARTHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
24 patentsUS7135724B2Nov 14, 2006
Structure and method for making strained channel field effect transistor using sacrificial spacer
IBM47 citations96
US7288482B2Oct 30, 2007
Silicon nitride etching methods
IBM260 citations95
US7176481B2Feb 13, 2007
In situ doped embedded sige extension and source/drain for enhanced PFET performance
IBM52 citations92
US7087532B2Aug 8, 2006
Formation of controlled sublithographic structures
IBM22 citations92
US6743727B2Jun 1, 2004
Method of etching high aspect ratio openings
IBM38 citations92
US7977185B2Jul 12, 2011
Method and apparatus for post silicide spacer removal
IBM9 citations84
US7709317B2May 4, 2010
Method to increase strain enhancement with spacerless FET and dual liner process
IBM15 citations84
US7525161B2Apr 28, 2009
Strained MOS devices using source/drain epitaxy
IBM17 citations84
US7459382B2Dec 2, 2008
Field effect device with reduced thickness gate
IBM9 citations84
US7645656B2Jan 12, 2010
Structure and method for making strained channel field effect transistor using sacrificial spacer
IBM7 citations74
US6709917B2Mar 23, 2004
Method to increase the etch rate and depth in high aspect ratio structure
IBM8 citations73
US7405436B2Jul 29, 2008
Stressed field effect transistors on hybrid orientation substrate
IBM6 citations72
US6706586B1Mar 16, 2004
Method of trench sidewall enhancement
IBM9 citations69
US7863197B2Jan 4, 2011
Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
IBM2 citations63
US7776695B2Aug 17, 2010
Semiconductor device structure having low and high performance devices of same conductive type on same substrate
IBM2 citations63
US7687829B2Mar 30, 2010
Stressed field effect transistors on hybrid orientation substrate
IBM4 citations63
US7186660B2Mar 6, 2007
Silicon precursors for deep trench silicon etch processes
IBM4 citations63
US7393746B2Jul 1, 2008
Post-silicide spacer removal
IBM6 citations62
US6806200B2Oct 19, 2004
Method of improving etch uniformity in deep silicon etching
IBM4 citations62
US7645356B2Jan 12, 2010
Method of processing wafers with resonant heating
IBM0 citations52
US7438822B2Oct 21, 2008
Apparatus and method for shielding a wafer from charged particles during plasma etching
IBM0 citations52
US7285775B2Oct 23, 2007
Endpoint detection for the patterning of layered materials
IBM0 citations51
US7278300B2Oct 9, 2007
Gas filled reactive atomic force microscope probe
IBM0 citations51
US7256399B2Aug 14, 2007
Non-destructive in-situ elemental profiling
IBM0 citations51
TOKYO ELECTRON LTD
3 patentsUS7754615B2Jul 13, 2010
Method and apparatus for detecting endpoint in a dry etching system by monitoring a superimposed DC current
TOKYO ELECTRON LTD4 citations62
US7344991B2Mar 18, 2008
Method and apparatus for multilayer photoresist dry development
TOKYO ELECTRON LTD6 citations60
US8048325B2Nov 1, 2011
Method and apparatus for multilayer photoresist dry development
TOKYO ELECTRON LTD1 citations44