P

Inventor

CHU CHIA-CHI

TW20 patents
⚠️ This page may combine multiple inventors who share the name “CHU CHIA-CHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

UNIV CHANG GUNG

18 patents
US7191418B2Mar 13, 2007

Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration

UNIV CHANG GUNG25 citations91
US7321834B2Jan 22, 2008

Method for calculating power flow solution of a power transmission network that includes interline power flow controller (IPFC)

UNIV CHANG GUNG45 citations90
US7216322B2May 8, 2007

Clock tree synthesis for low power consumption and low clock skew

UNIV CHANG GUNG20 citations90
US7177727B2Feb 13, 2007

Method for calculating power flow solution of a power transmission network that includes unified power flow controllers

UNIV CHANG GUNG47 citations90
US7813884B2Oct 12, 2010

Method of calculating power flow solution of a power grid that includes generalized power flow controllers

UNIV CHANG GUNG29 citations87
US7181664B2Feb 20, 2007

Method on scan chain reordering for lowering VLSI power consumption

UNIV CHANG GUNG14 citations83
US7254790B2Aug 7, 2007

Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops

UNIV CHANG GUNG8 citations72
US7562324B2Jul 14, 2009

Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization

UNIV CHANG GUNG4 citations61
US7373367B2May 13, 2008

Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter

UNIV CHANG GUNG3 citations61
US7216309B2May 8, 2007

Method and apparatus for model-order reduction and sensitivity analysis

UNIV CHANG GUNG6 citations61
US7124381B2Oct 17, 2006

Method of estimating crosstalk noise in lumped RLC coupled interconnects

UNIV CHANG GUNG7 citations61
US7017130B2Mar 21, 2006

Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits

UNIV CHANG GUNG7 citations61
US7600206B2Oct 6, 2009

Method of estimating the signal delay in a VLSI circuit

UNIV CHANG GUNG4 citations59
US7398499B2Jul 8, 2008

Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design

UNIV CHANG GUNG2 citations59
US7797140B2Sep 14, 2010

Generalizations of adjoint networks techniques for RLC interconnects model-order reductions

UNIV CHANG GUNG2 citations50
US7512525B2Mar 31, 2009

Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders

UNIV CHANG GUNG0 citations40
US7509243B2Mar 24, 2009

Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm

UNIV CHANG GUNG0 citations40
US7437689B2Oct 14, 2008

Interconnect model-order reduction method

UNIV CHANG GUNG0 citations40

UNIV NAT TSING HUA

1 patent

CHU CHIA-CHI

1 patent