Inventor

KUESEL JAMIE R

US33 patents

⚠️ This page may combine multiple inventors who share the name “KUESEL JAMIE R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUESEL JAMIE R

IBM

Dynamic thread status retrieval using inter-thread communication

Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor

Multiple spacial indexes for dynamic scene management in graphics rendering

Pixel color accumulation in a ray tracing image processing system

Network on chip that maintains cache coherency with invalidate commands

Network on chip that maintains cache coherency with invalidate commands

Dynamic load-based credit distribution

Dynamic thread status retrieval using inter-thread communication

Dynamic thread status retrieval using inter-thread communication

Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores

Graphics rendering on a network on chip

Preventing execution of software without a dynamically generated key

Dynamic thread status retrieval using inter-thread communication

Cache swizzle with inline transposition

Cache swizzle with inline transposition

Power distribution management in a system on a chip

Low-latency data decryption interface

Power distribution management in a system on a chip

Dynamic load-based credit distribution

Data encryption interface for reducing encrypt latency impact on standard traffic

Dynamic thread status retrieval using inter-thread communication

Dynamic thread status retrieval using inter-thread communication

Thread scheduling across heterogeneous processing elements with resource mapping

Thread scheduling across heterogeneous processing elements with resource mapping

Method and apparatus for providing high speed memory for a processing unit

Preventing execution of pirated software

KUESEL JAMIE R

Indirect inter-thread communication using a shared pool of inboxes

Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores

Regular expression searches utilizing general purpose processors on a network interconnect

Combined cache inject and lock operation

Branch prediction technique using instruction for resetting result table pointer

KRIEGEL JON K

Administering non-cacheable memory load instructions

BEUKEMA BRUCE L

Low-latency data decryption interface