Inventor

HAENSCH WILFRIED

US45 patents

⚠️ This page may combine multiple inventors who share the name “HAENSCH WILFRIED”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAENSCH WILFRIED

IBM

Fin field effect transistor devices with self-aligned source and drain regions

CMOS back-gated keeper technique

CMOS well structure and method of forming the same

Geometrical control of device corner threshold

Semiconductor structure including gate electrode having laterally variable work function

Geometrical control of device corner threshold

Four D device process and structure

Carbon nanotube array for cryptographic key generation and protection

Fin field effect transistor devices with self-aligned source and drain regions

Partially depleted SOI field effect transistor having a metallized source side halo region

Partially depleted SOI field effect transistor having a metallized source side halo region

Resistive random-access memory array with reduced switching resistance variability

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

Geometrical control of device corner threshold

Acceleration of convolutional neural networks on analog arrays

Inspection and identification to enable secure chip processing

Resistive random-access memory array with reduced switching resistance variability

Back-gate decode personalization

Hardware acceleration for computing eigenpairs of a matrix

Four D device process and structure

Eigenvalue decomposition with stochastic optimization

Resistive processing unit with multiple weight readers

Circuit methodology for differential weight reading in resistive processing unit devices

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

Semiconductor structure including gate electrode having laterally variable work function

Analog hardware matrix computation

Markov processes using analog crossbar arrays

Carbon nanotube array for cryptographic key generation and protection

Elemental semiconductor material contact for high indium content InGaN light emitting diodes

Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX)

CMOS back-gated keeper technique

CMOS well structure and method of forming the same

Extraction of weight values in resistive processing unit array

SIEMENS AG

Method for quantifying proximity effect by measuring device performance

Formation of silicided junctions in deep submicron MOSFETS by defect enhanced CoSi2 formation

Formation of silicided junctions in deep sub-micron MOSFETs by defect enhanced CoSi2 formation

Method of forming shallow junctions in field effect transistors

HAENSCH WILFRIED

4D device process and structure

Multigate structure formed with electroless metal deposition

Multigate structure formed with electroless metal deposition

BASKER VEERARAGHAVAN S

Method for fabricating finFET with merged fins and vertical silicide

finFET with merged fins and vertical silicide

CHANG JOSEPHINE B

Fin field effect transistor devices with self-aligned source and drain regions

YU ROY R

4D Device, process and structure

CHOU ANTHONY I

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)