Inventor
KAPOOR ASHOK KUMAR
US20 patents
⚠️ This page may combine multiple inventors who share the name “KAPOOR ASHOK KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SEMI SOLUTIONS LLC
6 patentsUS7586155B2Sep 8, 2009
Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
SEMI SOLUTIONS LLC16 citations92
US7224205B2May 29, 2007
Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
SEMI SOLUTIONS LLC17 citations92
US8048732B2Nov 1, 2011
Method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor
SEMI SOLUTIONS LLC10 citations82
US7691702B2Apr 6, 2010
Method of manufacture of an apparatus for increasing stability of MOS memory cells
SEMI SOLUTIONS LLC6 citations73
US7651905B2Jan 26, 2010
Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts
SEMI SOLUTIONS LLC3 citations62
US7375402B2May 20, 2008
Method and apparatus for increasing stability of MOS memory cells
SEMI SOLUTIONS LLC3 citations62
DSM SOLUTIONS INC
5 patentsUS7592841B2Sep 22, 2009
Circuit configurations having four terminal JFET devices
DSM SOLUTIONS INC25 citations92
US7560755B2Jul 14, 2009
Self aligned gate JFET structure and method
DSM SOLUTIONS INC12 citations83
US7474125B2Jan 6, 2009
Method of producing and operating a low power junction field effect transistor
DSM SOLUTIONS INC8 citations83
US7642566B2Jan 5, 2010
Scalable process and structure of JFET for small and decreasing line widths
DSM SOLUTIONS INC3 citations62
US7633101B2Dec 15, 2009
Oxide isolated metal silicon-gate JFET
DSM SOLUTIONS INC0 citations52
SUVOLTA INC
4 patentsUS7986167B2Jul 26, 2011
Circuit configurations having four terminal devices
SUVOLTA INC4 citations62
US7687335B2Mar 30, 2010
Self aligned gate JFET structure and method
SUVOLTA INC3 citations62
US7804332B2Sep 28, 2010
Circuit configurations having four terminal JFET devices
SUVOLTA INC0 citations51
US7941098B2May 10, 2011
Common data line signaling and method
SUVOLTA INC0 citations41
KAPOOR ASHOK KUMAR
3 patentsUS9147459B2Sep 29, 2015
Dynamic random access memories with an increased stability of the MOS memory cells
KAPOOR ASHOK KUMAR1 citations60
US9135977B2Sep 15, 2015
Random access memories with an increased stability of the MOS memory cell
KAPOOR ASHOK KUMAR3 citations60
US8247840B2Aug 21, 2012
Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode
KAPOOR ASHOK KUMAR1 citations48
SEMI SOLUTION LLC
2 patentsUS7683433B2Mar 23, 2010
Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
SEMI SOLUTION LLC50 citations95
US7898297B2Mar 1, 2011
Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits
SEMI SOLUTION LLC34 citations90