Inventor

SAMACHISA GEORGE

US85 patents

⚠️ This page may combine multiple inventors who share the name “SAMACHISA GEORGE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAMACHISA GEORGE

SANDISK CORP

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Method of reducing disturbs in non-volatile memory

Method of reducing disturbs in non-volatile memory

Processing techniques for making a dual floating gate EEPROM cell array

Dual floating gate EEPROM cell array with steering gates shared adjacent cells

Dual floating gate EEPROM cell array with steering gates shared by adjacent cells

Processing techniques for making a dual floating gate EEPROM cell array

Low voltage erase of a flash EEPROM system having a common erase electrode for two individual erasable sectors

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Non-volatile memory cells utilizing substrate trenches

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Steering gate and bit line segmentation in non-volatile memories

Dual floating gate EEPROM cell array with steering gates shared by adjacent cells

Memory array architecture utilizing global bit lines shared by multiple cells

Low voltage erase of a flash EEPROM system having a common erase electrode for two individually erasable sectors

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

Latent defect handling in EEPROM devices

Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Substrate electron injection techniques for programming non-volatile charge storage memory cells and for controlling program disturb

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Substrate electron injection techniques for programming non-volatile charge storage memory cells

Method of reducing disturbs in non-volatile memory

Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Floating gate memory cells utilizing substrate trenches to scale down their size

Method of reducing disturbs in non-volatile memory

Scalable self-aligned dual floating gate memory cell array and methods of forming the array

SANDISK 3D LLC

Memories with cylindrical read/write stacks

Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines

Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof

Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same

Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture

Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines

SANDISK TECHNOLOGIES INC

Method of making ultrahigh density vertical NAND memory device

Ultrahigh density monolithic, three dimensional vertical NAND memory device

Three dimensional NAND device with silicide containing floating gates

Method of making an ultrahigh density vertical NAND memory device with shielding wings

Operation modes for an inverted NAND architecture

Three dimensional NAND device with silicide containing floating gates and method of making thereof

SAMACHISA GEORGE

Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof

Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines

Junctionless TFT NAND flash memory

Non-volatile memory having 3D array of read/write elements with low current structures and methods thereof

SUNDISK CORP

Latent defect handling in EEPROM devices

ALSMEIER JOHANN

Method of making ultrahigh density vertical NAND memory device

SCHEUERLEIN ROY E

Temperature compensation of conductive bridge memory arrays

MIHNEA ANDREI

Punch-through diode steering element

FASOLI LUCA

Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture

RABKIN PETER

Memory system with reversible resistivity-switching using pulses of alternatrie polarity

SANDISK TECHNOLOGIES LLC

Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture