Inventor
PIERCE BERNARD
US11 patents
⚠️ This page may combine multiple inventors who share the name “PIERCE BERNARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
6 patentsUS8352950B2Jan 8, 2013
Algorithm to share physical processors to maximize processor cache usage and topologies
IBM2 citations62
US9262236B2Feb 16, 2016
Warning track interruption facility
IBM0 citations52
US9110741B2Aug 18, 2015
Warning track interruption facility
IBM0 citations52
US9104509B2Aug 11, 2015
Providing by one program to another program access to a warning track facility
IBM0 citations52
US9098358B2Aug 4, 2015
Use of a warning track interruption facility by a program
IBM0 citations52
US9098478B2Aug 4, 2015
Warning track interruption facility
IBM0 citations52
FARRELL MARK S
3 patentsUS8850450B2Sep 30, 2014
Warning track interruption facility
FARRELL MARK S3 citations62
US9110878B2Aug 18, 2015
Use of a warning track interruption facility by a program
FARRELL MARK S0 citations51
US9104508B2Aug 11, 2015
Providing by one program to another program access to a warning track facility
FARRELL MARK S0 citations51