Inventor

SANGHANI AMIT

US16 patents

⚠️ This page may combine multiple inventors who share the name “SANGHANI AMIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NVIDIA CORP

13 patents

US10281524B2May 7, 2019

Test partition external input/output interface control for test partitions in a semiconductor

NVIDIA CORP6 citations82

US10317463B2Jun 11, 2019

Scan system interface (SSI) module

NVIDIA CORP6 citations80

US9500706B2Nov 22, 2016

Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support

NVIDIA CORP3 citations70

US9395414B2Jul 19, 2016

System for reducing peak power during scan shift at the local level for scan based tests

NVIDIA CORP4 citations70

US9377510B2Jun 28, 2016

System for reducing peak power during scan shift at the global level for scan based tests

NVIDIA CORP5 citations70

US10444280B2Oct 15, 2019

Method and system for dynamic standard test access (DSTA) for a logic block reuse

NVIDIA CORP0 citations45

US9885753B2Feb 6, 2018

Scan systems and methods

NVIDIA CORP0 citations38

SANGHANI AMIT

2 patents

US8522190B1Aug 27, 2013

Power droop reduction via clock-gating for at-speed scan testing

SANGHANI AMIT12 citations82

US7305598B1Dec 4, 2007

Test clock generation for higher-speed testing of a semiconductor device

SANGHANI AMIT16 citations80

INTEL CORP

1 patent

US11257560B2Feb 22, 2022

Test architecture for die to die interconnect for three dimensional integrated circuits

INTEL CORP1 citations55

SANGHANI AMIT

NVIDIA CORP

Test partition external input/output interface control for test partitions in a semiconductor

Scan system interface (SSI) module

Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support

System for reducing peak power during scan shift at the local level for scan based tests

System for reducing peak power during scan shift at the global level for scan based tests

Independent test partition clock coordination across multiple test partitions

Performing on-chip partial good die identification

Granular dynamic test systems and methods

Dynamic independent test partition clock

Granular dynamic test systems and methods

Virtual access of input/output (I/O) for test via an on-chip star network

Method and system for dynamic standard test access (DSTA) for a logic block reuse

Scan systems and methods

SANGHANI AMIT

Power droop reduction via clock-gating for at-speed scan testing

Test clock generation for higher-speed testing of a semiconductor device

INTEL CORP

Test architecture for die to die interconnect for three dimensional integrated circuits