Inventor
KRITHIVAS RAMAMURTHY
US31 patents
⚠️ This page may combine multiple inventors who share the name “KRITHIVAS RAMAMURTHY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
27 patentsUS6816963B1Nov 9, 2004
Platform level initialization using an image generated automatically by a remote server based upon description automatically generated and transmitted thereto by a processor-based system
INTEL CORP122 citations94
US6067628AMay 23, 2000
Method to monitor universal serial bus hub overcurrent
INTEL CORP93 citations94
US7516252B2Apr 7, 2009
Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment
INTEL CORP44 citations92
US7349999B2Mar 25, 2008
Method, system, and program for managing data read operations on network controller with offloading functions
INTEL CORP18 citations92
US9535606B2Jan 3, 2017
Virtual serial presence detect for pooled memory
INTEL CORP12 citations83
US7454603B2Nov 18, 2008
Method and system for linking firmware modules in a pre-memory execution environment
INTEL CORP8 citations73
US10048744B2Aug 14, 2018
Apparatus and method for thermal management in a multi-chip package
INTEL CORP2 citations72
US9996711B2Jun 12, 2018
Asset protection of integrated circuits during transport
INTEL CORP5 citations72
US9686143B2Jun 20, 2017
Mechanism for management controllers to learn the control plane hierarchy in a data center environment
INTEL CORP3 citations71
US6014511AJan 11, 2000
O/S abstraction architecture for HID PC applications
INTEL CORP11 citations70
US10222823B2Mar 5, 2019
Computing apparatus with real time clock without a battery
INTEL CORP3 citations69
US7664892B2Feb 16, 2010
Method, system, and program for managing data read operations on network controller with offloading functions
INTEL CORP2 citations62
US12079153B2Sep 3, 2024
Dynamic configuration of input/output controller access lanes
INTEL CORP0 citations61
US11693807B2Jul 4, 2023
Dynamic configuration of input/output controller access lanes
INTEL CORP0 citations61
US10956351B2Mar 23, 2021
Dynamic configuration of input/output controller access lanes
INTEL CORP0 citations61
US10762006B2Sep 1, 2020
Techniques to dynamically enable memory channels on a compute platform
INTEL CORP1 citations58
US10509435B2Dec 17, 2019
Protected real time clock with hardware interconnects
INTEL CORP1 citations56
US11874787B2Jan 16, 2024
Platform controller hub (PCH) chipsets in platforms as extended IO expander(s)
INTEL CORP0 citations53
US11157064B2Oct 26, 2021
Techniques to dynamically enable and disable accelerator devices in compute environments
INTEL CORP0 citations51
US10628615B2Apr 21, 2020
Asset protection of integrated circuits during transport
INTEL CORP0 citations51
US10223161B2Mar 5, 2019
Hardware-based inter-device resource sharing
INTEL CORP0 citations51
US9703697B2Jul 11, 2017
Sharing serial peripheral interface flash memory in a multi-node server system on chip platform environment
INTEL CORP1 citations51
US9569267B2Feb 14, 2017
Hardware-based inter-device resource sharing
INTEL CORP0 citations51
US11294749B2Apr 5, 2022
Techniques to collect crash data for a computing system
INTEL CORP0 citations50
US10116518B2Oct 30, 2018
Mechanism for management controllers to learn the control plane hierarchy in a data center environment
INTEL CORP0 citations50
US12411689B2Sep 9, 2025
Method to reduce register access latency in split-die SoC designs
INTEL CORP0 citations42
US9817787B2Nov 14, 2017
Method, apparatus and system for encapsulating information in a communication
INTEL CORP0 citations40