Inventor
TAVARES ANDREA IABRUDI
BR5 patents
Patents
5 patentsUS10204201B1Feb 12, 2019
Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques
CADENCE DESIGN SYSTEMS INC12 citations79
US10094875B1Oct 9, 2018
Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design
CADENCE DESIGN SYSTEMS INC2 citations71
US9633151B1Apr 25, 2017
Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths
CADENCE DESIGN SYSTEMS INC5 citations68
US9817930B1Nov 14, 2017
Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow
CADENCE DESIGN SYSTEMS INC6 citations64
US10769008B1Sep 8, 2020
Systems and methods for automatic formal metastability fault analysis in an electronic design
CADENCE DESIGN SYSTEMS INC1 citations48