Inventor

SEIDEMANN GEORG

DE86 patents

⚠️ This page may combine multiple inventors who share the name “SEIDEMANN GEORG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SEIDEMANN GEORG

INTEL CORP

Microelectronic package having a passive microelectronic device disposed within a package body

Antenna on ceramics for a packaged die

Magnetic contacts

Package stacking using chip to wafer bonding

Bare-die smart bridge connected with copper pillars for system-in-package apparatus

Package stacking using chip to wafer bonding

Printed wiring-board islands for connecting chip packages and methods of assembling same

Fan out packaging pop mechanical attach method

Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

Contact pads for integrated circuit packages

Method to implement wafer-level chip-scale packages with grounded conformal shield

Assembly of 2XD module using high density interconnect bridges

Bare-die smart bridge connected with copper pillars for system-in-package apparatus

Assembly of 2XD module using high density interconnect bridges

Vertical and lateral interconnects between dies

Interconnect structure for stacked die in a microelectronic device

Fan out packaging pop mechanical attach method

Microelectronic assemblies having topside power delivery structures

Antenna with graded dielectirc and method of making the same

Printed wiring-board islands for connecting chip packages and methods of assembling same

Systems, methods, and apparatuses for implementing reduced height semiconductor packages for mobile electronics

Magnetic coils in locally thinned silicon bridges and methods of assembling same

Wafer level package structure with internal conductive layer

Semiconductor inductors

Stress relief die implementation

Magnetic contacts

Magnetic contacts

Substrate for improved heat dissipation and method

Method to implement wafer-level chip-scale packages with grounded conformal shield

Semiconductor dies and devices with frontside and backside coils for inductive coupling

INTEL IP CORP

System-in-package devices and methods for forming system-in-package devices

Integrated circuit package assemblies including a chip recess

Semiconductor device with capacitive coupling structure

Integrated circuit package assemblies including a chip recess

Electrical device and a method for forming an electrical device

Integrated circuit packages including an optical redistribution layer

Antenna with graded dielectirc and method of making the same

Die edge side connection

Semiconductor package having a variable redistribution layer thickness

Semiconductor package having a variable redistribution layer thickness

Integrated circuit package configurations to reduce stiffness

Lead frame with angular deflections and wrapped printed wiring boards for system-in-package apparatus

Wafer level package structure with internal conductive layer

Interposer with conductive routing exposed on sidewalls

Power mesh-on-die trace bumping

Vertical wire connections for integrated circuit package

Interconnect structure for a microelectronic device

Power mesh-on-die trace bumping

Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

MARUTHAMUTHU SARAVANA

Bulk acoustic wave resonator tuner circuits