Inventor

LI WAI-KIN

US123 patents

⚠️ This page may combine multiple inventors who share the name “LI WAI-KIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI WAI-KIN

IBM

Sub-lithographic interconnect patterning using self-assembling polymers

Sub-lithographic feature patterning using self-aligned self-assembly polymers

Sub-lithographic local interconnects, and methods for forming same

Sub-lithographic nano interconnect structures, and method for forming same

Method for fabricating shallow trench isolation structures using diblock copolymer patterning

Dual damascene metal interconnect structure having a self-aligned via

Sub-lithographic gate length transistor using self-assembling polymers

On-chip semiconductor device having enhanced variability

On-chip structure for security application

Electronic fuse having a damaged region

Method for reducing tip-to-tip spacing between lines

Gate conductor structure

Sub-lithographic dimensioned air gap formation and related structure

Photoresist compositions and method for multiple exposures with multiple layer resist systems

Photoresist compositions and method for multiple exposures with multiple layer resist systems

Electrical fuse having sublithographic cavities thereupon

Non-planar fuse structure including angular bend

Electrical fuses and resistors having sublithographic dimensions

Contact aperture and contact via with stepped sidewall and methods for fabrication thereof

Empty vias for electromigration during electronic-fuse re-programming

Method and structure for ultra narrow crack stop for multilevel semiconductor device

Structure of power grid for semiconductor devices and method of making the same

Apparatus and method to improve resist line roughness in semiconductor wafer processing

Bridging local semiconductor interconnects

Utilizing inverse reactive ion etching lag in double patterning contact formation

Electrical fuse having sublithographic cavities thereupon

Microelectronic circuit structure with layered low dielectric constant regions and method of forming same

Fully and uniformly silicided gate structure and method for forming same

Circuit structure with low dielectric constant regions and method of forming same

Strained MOSFETs on separated silicon layers

Embedded on-chip security

Embedded on-chip security

Si-containing polymers for nano-pattern device fabrication

CHENG JOY

Method of forming sub-lithographic features using directed self-assembly of polymers

Method for designing optical lithography masks for directed self-assembly

Method for designing optical lithography masks for directed self-assembly

Directed self-assembly of block copolymers using segmented prepatterns

GLOBALFOUNDRIES INC

On-chip finFET structures to implement physical unclonable function for security application

Inducing device variation for security applications

Dynamic alignment by electrical potential and flow control to single-wall carbon nanotube field effect transistors

Integration process to form microelectronic or micromechanical structures

CHEN KUANG-JUNG

Method for removing threshold voltage adjusting layer with external acid diffusion process

LI WAI-KIN

Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques

YANG CHIH-CHAO

Method of fabricating a profile control in interconnect structures

WANG PING-CHUAN

Structure of metal e-fuse

GLODDE MARTIN

Near-infrared absorbing film compositions

PARK O SEO

Methods of manufacturing semiconductor devices and optical proximity correction

FILIPPI RONALD

Structure of power grid for semiconductor devices and method of making the same

FENG KAI D

Method for fabricating a physical unclonable interconnect function array

CHOI SAMUEL S

Lateral-dimension-reducing metallic hard mask etch