Inventor
SHUR ROBERT D
US11 patents
⚠️ This page may combine multiple inventors who share the name “SHUR ROBERT D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VLSI TECHNOLOGY INC
9 patentsUS5956257ASep 21, 1999
Automated optimization of hierarchical netlists
VLSI TECHNOLOGY INC77 citations96
US5402356AMar 28, 1995
Buffer circuit design using back track searching of site trees
VLSI TECHNOLOGY INC23 citations92
US5402357AMar 28, 1995
System and method for synthesizing logic circuits with timing constraints
VLSI TECHNOLOGY INC43 citations92
US5197015AMar 23, 1993
System and method for setting capacitive constraints on synthesized logic circuits
VLSI TECHNOLOGY INC35 citations92
US5068812ANov 26, 1991
Event-controlled LCC stimulation
VLSI TECHNOLOGY INC37 citations92
US5062067AOct 29, 1991
Levelized logic simulator with fenced evaluation
VLSI TECHNOLOGY INC30 citations92
US5483544AJan 9, 1996
Vector-specific testability circuitry
VLSI TECHNOLOGY INC8 citations73
US5295088AMar 15, 1994
Method for predicting capacitance of connection nets on an integrated circuit
VLSI TECHNOLOGY INC10 citations73
US5193092AMar 9, 1993
Integrated parity-based testing for integrated circuits
VLSI TECHNOLOGY INC17 citations69