Inventor

WEBB CHARLES FRANKLIN

US39 patents

⚠️ This page may combine multiple inventors who share the name “WEBB CHARLES FRANKLIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEBB CHARLES FRANKLIN

IBM

System serialization with early release of individual processor

Multiprocessor serialization with early release of processors

Method and apparatus for active software disown of cache line&#39;s exlusive rights

Specialized millicode instruction for translate and test

Mapping processor state into a millicode addressable processor state register array

Millicode load and test access instruction that blocks interrupts in response to access exceptions

Specialized millicode instructions which reduce cycle time and number of instructions necessary to perform complex operations

Specialized millicode instructions for test PSW validity, load with access test, and character translation assist

Implementation of binary floating point using hexadecimal floating point unit

System for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operation

Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all

Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer

Avoiding processor serialization after an S/390 SPKA instruction

Demote instruction for relinquishing cache line ownership

Computer with optimizing hardware for conditional hedge fetching into cache storage

Linking program access register number with millicode operand access

Specialized millicode instructions for packed decimal division

Specialized millicode instruction for editing functions

Cache memory accessed by continuation requests

System speed loading of a writable cache code array

Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code

Computer processor system for executing RXE format floating point instructions

Millicode flags with specialized update and branch instructions

Hardware retry trap for millicoded processor

Addressing extended memory using millicode by concatenating a small millicode address and address extension data

Millicode extended memory addressing using operand access control register to control extended address concatenation

Computer processor system for implementing the ESA/390 STOSM and STNSM instructions without serialization or artificially extending processor execution time

Demote instruction for relinquishing cache line ownership

Demote instruction for relinquishing cache line ownership

Method for conditional hedge fetching into cache storage

Method for Quad-word Storing into 2-way interleaved L1 cache

Method for use in translating virtual addresses into absolute addresses

Specialized millicode instruction for certain decimal operations

Demote instruction for relinquishing cache line ownership

Demote instruction for relinquishing cache line ownership

Demote instruction for relinquishing cache line ownership

Demote instruction for relinquishing cache line ownership

System for use in translating virtual addresses into absolute addresses

SHUM CHUNG-LUNG KEVIN

Computer system having cache subsystem performing demote requests

Method and apparatus for active software disown of cache line's exlusive rights