Inventor

KYKER ALAN B

US37 patents

⚠️ This page may combine multiple inventors who share the name “KYKER ALAN B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KYKER ALAN B

INTEL CORP

Method and apparatus for thread switching within a multithreaded processor

Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction

Method and apparatus for power mode transition in a multi-thread processor

System and method of maintaining and utilizing multiple return stack buffers

Method and apparatus for thread switching within a multithreaded processor

Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction

Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread

System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units

System and method of maintaining and utilizing multiple return stack buffers

Determination of approaching instruction starvation of threads based on a plurality of conditions

Branch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction pool

Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction

Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor

Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction information

System and method for storing immediate data

Method and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessor

Method and apparatus for performing sequential executions of elements in cooperation with a transform

Determining whether thread fetch operation will be blocked due to processing of another thread

Method and system for an INUSE field resource management scheme

Systems and methods for synergistic software-hardware power budget management

Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table

Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition

Updating stack pointer based on instruction bit indicator without executing an update microinstruction

Method and apparatus for power mode transition in a multi-thread processor

System and method for storing immediate data

System and method for storing immediate data

Systems and methods for synergistic software-hardware power budget management

Detection, recovery and prevention of bogus branches

Method and apparatus for power mode transition in a multi-thread processor

Single cycle linear address calculation for relative branch addressing

Single cycle linear address calculation for relative branch addressing

System and method for storing immediate data

Systems and methods for synergistic software-hardware power budget management

Method and system for an INUSE field resource management scheme

System and method for storing immediate data

Data transfer between asynchronous clock domains

RIFANI MICHAEL C

Data transfer between asynchronous clock domains