Inventor

HOLLMER SHANE C

US30 patents

⚠️ This page may combine multiple inventors who share the name “HOLLMER SHANE C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOLLMER SHANE C

ADVANCED MICRO DEVICES INC

Method of maintaining constant erasing speeds for non-volatile memory cells

Erase verify scheme for NAND flash

Scheme for page erase and erase verify in a non-volatile memory array

Programmed reference

Global erase/program verification apparatus and method

Sidewall NROM and method of manufacture thereof for non-volatile memory cells

Memory system having a program and erase voltage modifier

Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device

Boosted and regulated gate power supply with reference tracking for multi-density and low voltage supply memories

Double boosting scheme for NAND to improve program inhibit characteristics

Select transistor architecture for a virtual ground non-volatile memory cell array

Embedded methodology to program/erase reference cells used in sensing flash cells

Continuous capacitor divider sampled regulation scheme

Floating gate capacitor for use in voltage regulators

Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same

Multistepped threshold convergence for a flash memory array

Method and apparatus for adjusting on-chip current reference for EEPROM sensing

Erase verify mode to evaluate negative Vt&#39;s

EEPROM decoder block having a p-well coupled to a charge pump for charging the p-well and method of programming with the EEPROM decoder block

Split voltage for NAND flash

Reduced column leakage during programming for a flash memory array

Programmable current source

Array VSS biasing for NAND array programming reliability

Two side decoding of a memory array

EMOSYN AMERICA INC

Method and apparatus for avoiding gated diode breakdown in transistor circuits

Method and apparatus for emulating an electrically erasable programmable read only memory (EEPROM) using non-volatile floating gate memory cells

Method and apparatus for detecting exposure of a semiconductor circuit to ultra-violet light

KAMALANATHAN DEEPAK

Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse

ADESTO TECH CORP

Resistive memory device with ramp-up/ramp-down program/erase pulse

ADESTO TECHNOLOGIES CORP

Safeguarding data through an SMT process

Erase verify mode to evaluate negative Vt's