Inventor
SAFFORD KEVIN DAVID
US25 patents
⚠️ This page may combine multiple inventors who share the name “SAFFORD KEVIN DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEWLETT PACKARD DEVELOPMENT CO
23 patentsUS7370232B2May 6, 2008
Method and apparatus for recovery from loss of lock step
HEWLETT PACKARD DEVELOPMENT CO98 citations98
US7085959B2Aug 1, 2006
Method and apparatus for recovery from loss of lock step
HEWLETT PACKARD DEVELOPMENT CO66 citations98
US7343479B2Mar 11, 2008
Method and apparatus for implementing two architectures in a chip
HEWLETT PACKARD DEVELOPMENT CO18 citations92
US6820190B1Nov 16, 2004
Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions
HEWLETT PACKARD DEVELOPMENT CO29 citations92
US6681322B1Jan 20, 2004
Method and apparatus for emulating an instruction set extension in a digital computer system
HEWLETT PACKARD DEVELOPMENT CO24 citations92
US7296181B2Nov 13, 2007
Lockstep error signaling
HEWLETT PACKARD DEVELOPMENT CO22 citations91
US7237144B2Jun 26, 2007
Off-chip lockstep checking
HEWLETT PACKARD DEVELOPMENT CO43 citations91
US7155721B2Dec 26, 2006
Method and apparatus for communicating information between lock stepped processors
HEWLETT PACKARD DEVELOPMENT CO23 citations90
US7139936B2Nov 21, 2006
Method and apparatus for verifying the correctness of a processor behavioral model
HEWLETT PACKARD DEVELOPMENT CO16 citations90
US7003691B2Feb 21, 2006
Method and apparatus for seeding differences in lock-stepped processors
HEWLETT PACKARD DEVELOPMENT CO32 citations90
US6625759B1Sep 23, 2003
Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit
HEWLETT PACKARD DEVELOPMENT CO22 citations90
US7290169B2Oct 30, 2007
Core-level processor lockstepping
HEWLETT PACKARD DEVELOPMENT CO39 citations89
US6609247B1Aug 19, 2003
Method and apparatus for re-creating the trace of an emulated instruction set when executed on hardware native to a different instruction set field
HEWLETT PACKARD DEVELOPMENT CO35 citations85
US7287185B2Oct 23, 2007
Architectural support for selective use of high-reliability mode in a computer system
HEWLETT PACKARD DEVELOPMENT CO18 citations84
US6643800B1Nov 4, 2003
Method and apparatus for testing microarchitectural features by using tests written in microcode
HEWLETT PACKARD DEVELOPMENT CO18 citations81
US6807625B1Oct 19, 2004
Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions
HEWLETT PACKARD DEVELOPMENT CO7 citations74
US6745322B1Jun 1, 2004
Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition
HEWLETT PACKARD DEVELOPMENT CO12 citations74
US6789186B1Sep 7, 2004
Method and apparatus to reduce penalty of microcode lookup
HEWLETT PACKARD DEVELOPMENT CO8 citations73
US6618801B1Sep 9, 2003
Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information
HEWLETT PACKARD DEVELOPMENT CO10 citations73
US6542862B1Apr 1, 2003
Determining register dependency in multiple architecture systems
HEWLETT PACKARD DEVELOPMENT CO10 citations73
US7725899B2May 25, 2010
Method and apparatus for communicating information between lock stepped processors
HEWLETT PACKARD DEVELOPMENT CO4 citations60
US7398419B2Jul 8, 2008
Method and apparatus for seeding differences in lock-stepped processors
HEWLETT PACKARD DEVELOPMENT CO4 citations60
US6668315B1Dec 23, 2003
Methods and apparatus for exchanging the contents of registers
HEWLETT PACKARD DEVELOPMENT CO1 citations52